The Qsys-compliant certification is awarded to intellectual property (IP) cores that seamlessly integrate with the Platform Designer (formerly Qsys) included in the Quartus® II or Intel® Quartus Prime design software. Qsys-compliant cores support industry-standard interconnect interfaces including Avalon® Memory-Mapped (Avalon-MM), Avalon Streaming (Avalon-ST), ARM* AXI3*, AXI4*, AXI4-lite*, AXI4 Stream*, APB*, and AHB*.
Visit the online IP catalog for an up-to-date list of Qsys-compliant IP cores.
Qsys-Compliant IP Core Deliverables
An IP core must meet the following requirements to achieve the Qsys-compliant certification:
- Interface to the system interconnect fabric via one of the industry-standard interconnect interfaces listed above
- Platform Designer (formerly Qsys) plug-and-play integration via hw.tcl
Intel FPGA Design Solutions Network members can certify their IP cores as Qsys compliant as long as they meet the above-mentioned requirements.
Qsys-compliant IP cores have been verified with an Avalon Monitor component on each Avalon-ST or Avalon-MM interface, and have no protocol violations.
Hardware Design Example
The IP core also includes a design example created with the Platform Designer (formerly Qsys), to illustrate the correct interaction of the IP core with the Platform Designer (formerly Qsys).