Intel® FPGA IP cores deliver the highest performance, lowest latency, and smallest resource utilization in the FPGA industry. The IP portfolio includes Ethernet, Interlaken, Interlaken Look-Aside, PCI Express*, and External Memory Interface IP cores. Intel splashed onto the scene with Interlaken and Ethernet cores, providing industry-leading lowest latency and resource utilization. PCI Express IP provides unmatched, bar-raising throughput and input/output operations per second (IOPS) performance. On the memory interface front, the External Memory Interface IP delivers highest 2,400 Mbps DDR4 SDRAM performance in 20 nm devices, with lowest power and programmable logic use. †
Intel® Arria® 10 devices achieve PCI-SIG* compliance with perfect marks. 100% compliant - interoperability testing and compliance testing. These results bode well for Intel FPGAs customers by reducing technology system risks as well as design cycle times. For access to Arria 10 PCI-SIG compliance reports, please contact your local sales or distributor representative.
Not only is the IP compliant, but Intel FPGA PCI Express* IP solution delivers knockout performance to exceed ever-increasing demand end-user applications. The PCI Express IP solution maximizes throughput and IOPS performance, enabling you to extend your market leadership. The PCI Express IP solution includes a newly architected direct memory access (DMA) engine, enterprise-ready device drivers, and reference designs that greatly simplify the evaluation and design integration process.
For more information, visit the PCI Express IP product web page.
See the demonstrated throughput and IOPS performance of Intel FPGA PCI Express IP solution for both Arria 10 and Stratix® V devices.
PCI Express IP Performance Demonstration on Arria 10
PCI Express IP Performance Demonstration on Stratix V
Intel FPGA External Memory Interface (EMIF) IP offers memory interface performance, with DDR4 2,400 Mbps support for 20 nm devices in the Arria 10 device family.
The value you get from Arria 10 external memory interface IP extends beyond performance and throughput. Intel simplifies the development of Arria 10-based systems that feature DDR4, DDR3, and LPDDR3 memories by integrating a complete physical interface and hard memory controller into the FPGA. Aside from delivering higher performance and bandwidth, this hardened memory controller approach enables you to save power in your systems and eliminates the use of programmable logic resources to build the memory controller.
On top of all that, you will be able to use a host of usability features, such as BluePrint, Traffic Generator 2.0, and Driver Margining, when implementing memory interfaces with Arria 10 devices.
All in all, Arria 10 devices deliver 2,400 Mbps DDR4 SDRAM performance with the highest ease-of-use. For more information, visit the External Memory Interface IP product web page.
See the following engineer-to-engineer videos on several new usability features introduced into the Intel Quartus® Prime design software over the past few releases.
Intel FPGA Ethernet IP cores cover the range and requirements of all types of systems, from in-vehicle driver assistance to network attached storage systems. From commonly used 10 Mbps to 100 Gbps and new data rates like 2.5G and 25G Ethernet, Intel has the right IP to fit your design needs. All of our IP cores comply with the IEEE 802.3 standard and support IEEE 1588v2 time stamping. Options for Reed Solomon Forward Error Correction (RS - FEC) and Backplane support are also available. For more information on our Ethernet IP cores, visit the Ethernet IP portfolio web page.
Get a special sneak peek at our pre-standard 400G Ethernet IP!
Jump ahead of the pack with Intel FPGA 300G Interlaken and Interlaken Look-Aside IP. These IP cores help you transform your next-generation architectures by providing 2X more bandwidth and a 10% latency reduction versus existing 100G/150G Interlaken-based communications systems†. By integrating these IP into your systems, together we are enabling networks to handle the vast amounts of data movements that the world requires.
Intel’s FPGA-based Interlaken and Interlaken Look-Aside IP solutions are chip-to-chip protocols for packet transfer applications. These IP cores were built on an architecture that provides high performance, latency, and logic resourcing. The Interlaken and Interlaken Look-Aside IP cores consist of soft and hardened logic blocks that offer you a high degree of user interface, lane, and data rate configuration flexibility for optimal integration.
Experience the turbocharged throughput and low latency of Intel FPGA Interlaken Look-Aside IP core on Arria 10 devices.
300G Interlaken Look-Aside IP Performance Interop with TE
Connectivity using Arria 10
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.