SDI II IP Core

From Intel® (formerly Altera)

The serial digital interface (SDI) II intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers.  The SDI II IP core supports dual standard, triple standard, and multi standard. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

The SDI II IP core highlights the following new features:

  • IEEE encryption for functional simulation across a variety of tools
  • Dynamic generation of user simulation testbench that matches the IP configuration
  • Dynamic generation of design example that serves as common entity for simulation and hardware verification

NAB 2016: Robust 4K60 transport over a single 12G SDI link

SMPTE ST-2082 demonstration in Arria 10

IP Core Feature

Description

Transceiver data interface

20 bit and 80 bit

Supported SDI standards and video formats

  • Single Standard
    • Standard Definition or SD-SDI
    • High Definition or HD-SDI
    • 3 gigabits per second (Gbps) or 3G-SDI
    • Dual Link HD-SDI
  • Multiple Standards
    • Dual Standard up to HD-SDI
    • Triple Standard up to 3G-SDI
    • Multi Standard up to 12G-SDI

Note: Not all devices support all formats, see “Device Support” below

SMPTE support

  • SMPTE425M level A support (direct source image formatting)
  • SMPTE425M level B support (dual link mapping)

Other features

  • Payload identification packet insertion and extraction
  • Clock enable generator
  • Video rate detection
  • Cyclic redundancy check (CRC) encoding and decoding (except SD)
  • Dual link data stream synchronization (only HD)
  Single Standard
Multiple Standards
Device Family
SD-SDI HD-SDI
3G-SDI

Dual Link

HD-SDI

Dual Standard

(up to HD)

Triple Standard

(up to 3G)

Multi Standard

(up to 12G)

Arria® 10 No Yes Yes Yes No Yes Yes
Stratix® V Yes Yes Yes Yes Yes Yes No
Arria V GX Yes Yes Yes Yes Yes Yes No
Arria V GZ
Yes Yes Yes Yes Yes Yes No
Cyclone® V
Yes Yes Yes Yes Yes Yes No

For previous generation device support, visit the SDI MegaCore Function Support Center.

Basics

Year IP was first released

2006

Latest version of Quartus® software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file

  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for OpenCore Plus Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Other (Parallel Video)

IP-XACT metadata

No

Verification

Simulators supported

ModelSim, VCS, Riviera-PRO, NCSim

Hardware validated

Arria 10, Arria V GX/GZ, Cyclone V, Stratix V

Industry standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Arria V, Stratix V, Arria 10

Interoperability reports available

Contact Sales

Design Examples and Development Kits

The following design examples are available for you to run on our development kits.

Video Tutorials

The following video tutorials are available for you to learn about using this IP.

Videos Description

SDI II IP Step-by -Step Implementation Guide for an Intel FPGA Arria 10 Device (8 min)

This video demonstrates how to implement an Intel FPGA SDI II IP core in an Arria 10 device. You will be guided through step by step generation in Quartus II software for all necessary transceiver related components and integration.

SDI II dynamic TX clock switching feature implementation and hardware verification (4 min)

This video provides theory of operation and a demonstration of the implementation of the SDI II dynamic TX clock switching capability for Arria 10 devices.

Additional support for these MegaCore functions is available in the mySupport online issue tracking system.