SerialLite III Streaming Protocol

From Intel (formerly Altera)

Figure 1. Typical Application Block Diagram

1st Level SignalTap™ IP Debug Feature

Push-button Hardware Design Examples in Quartus® Prime

SerialLite III Streaming intellectual property (IP) continues to scale with today's demand for more bandwidth and higher performance needs. SerialLite III is a simple, low latency, scalable protocol for high-bandwidth serial data transfer applications. SerialLite III offers simple connectivity that enables rapid point-to-point data transfers across various transmission media, including printed circuit board (PCB), backplane, copper cabling, and fiber optics.

Intel FPGA SerialLite III Streaming IP Solution

The SerialLite III Streaming IP function includes Intel’s technology-leading transceivers: physical medium attachment (PMA), phyiscal coding sublayer (PCS), and media access control (MAC) layers. The PCS and PMA layers are hardened within the Stratix® 10, Arria® 10, Stratix V, and Arria V FPGAs, thereby saving customers 30% to 50% of FPGA logic resources. In addition to resource savings, the hardened PCS/PMA functionality enables much easier timing closure for all types of designs. The SerialLite III protocol was designed to provide the necessary reliability, low latency and overhead, and scalability to ensure that data is transferred in the most efficient and robust manner to maintain low bit error rates required by today’s and next generation systems.

For more information, please contact your local Intel FPGA sales representative or email SLIII@altera.com.

Table 1. Performance and Productivity You Can Expect

Performance Productivity
Data efficiency rated as high as 95% 15% IP core timing margin accelerates full design timing closure
Over 300 Gbps of aggregate bandwidth for current and emerging applications (up to 24 lanes) OpenCore Plus feature allows you to test drive IP for free and without a license
Low latency data transfers (< 150 ns: TX + RX) Fully integrated SerialLite III IP includes MAC, PCS, and PMA layers for ease of FPGA IP integration
AC and DC coupling allows flexibility to tune lane(s) for improved bit error rates  
  • Data rate selection up to 17.4 Gbps
  • Multi-lane configuration up to 24 lanes
  • Data streaming operations - continuous or bursty
  • Simplex and full duplex operations
  • Flexible user clocking modes
  • Hardened resource utilization advantage
  • Low-latency data transfer (< 150 ns: TX + RX)
  • Minimized transmission overhead (< 4%)
  • 64B/67B encoding/decoding scheme
  • Optional error correction code (ECC) support on M20K's (SEU mitigation)
  • Optional error injection or detection and health monitoring
  • Fully integrated IP (MAC, PCS, and PMA layers)
  • Tunable pre-emphasis and equalization settings
  • Support for both AC and DC coupling

Intel FPGA SerialLite III Streaming IP core is supported on the following device families:

Table 2. SerialLite III Streaming IP Quality Metrics

Basics

Year IP was first released

2013

Latest version of the Quartus® software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim* - Intel® FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file
Y for all, except for providing Readme file

Any additional customer deliverables provided with IP

Testbench and Design Examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for OpenCore Plus Support

Y

Source language

Verilog and VHDL

Testbench language

Verilog

Software drivers provided

N

Driver OS Support

N

Implementation

User interface

Avalon® Streaming

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS/VCSMX

Hardware validated

Y, Arria 10 Transceiver Signal Integrity Development Kit

Industry standard compliance testing performed

N

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Stratix V and Arria 10 GX

Interoperability reports available

N

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