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The v15.1 release of Quartus® Prime design software features new additions and feature enhancements to the MegaCore® IP portfolio. Click on the images below to learn about some of the exciting new features. For more information and a complete list of feature enhancements, visit our What's New in IP web page.


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Interlaken Look-Aside 

Altera delivers all intellectual property (IP) as MegaCore® IPs that are built into the Quartus® Prime software. The portfolio includes IP for protocol and memory interfaces, digital signal processing (DSP), embedded processors, and related peripherals. The MegaCore IP Library is included in Quartus Prime Lite Edition, Quartus Prime Standard Edition and Quartus Prime Pro Edition. 

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New Feature Additions and Enhancements

The v15.1 release of Quartus® Prime design software features new additions and feature enhancements to the MegaCore® IP portfolio. 


All MegaCore* IPs can be used in Pro, Standard, and Lite Editions of Quartus® Prime software. The product page for each Altera IP core details its features and benefits including release-specific enhancements. For more details on Quartus Prime design software updates, visit the What's New in Quartus Prime page.

New Out-of-the-Box Design Examples

  • Preconfigured to target Altera development kit
  • Updated design example GUI with increased usability features:
    • Added tabs for improved parameter editing flow
    • Push-button generation of all necessary design example files
    • Updated documentation links and parameter description window
  • Check out the "Push-button hardware design examples in Quartus Prime" video to see how these design examples provide an out-of-the-box hardware verification platform

IP Infrastructure Improvements:

  • Spectra-Q™ industry-standard Verilog and mixed language synthesis for all IP
  • Seamless licensing for Quartus® Prime Standard and Pro Editions
  • Click-through IP upgrade notifications with color-coded status indicator in Project Navigator window

External Memory Interfaces:

  • Improved debug and diagnostics for EMIF Debug Toolkit featuring:
    • New 2D eye diagram for EMIF Debug Toolkit
    • New GUI options for Configurable Traffic generator 2.0 for improved flexibility and dynamic reconfiguration
    • Improved application programming interface (API) for On-Chip Debug Toolkit
    • Automated memory ODT sweep
  • New hardware verified MegaCore IPs
    • DDR x4 LRDIMM
    • QDR II and QDR+Xtreme
    • QDRIV – Now supporting 1,066 MHz
  • Hybrid Memory Cube Controller (HMCC) feature upgrades include:
    • Added Altera Debug Master Endpoint (ADME) support
    • Support for Multi Transaction All Packet Size (MTAPS) for full bandwidth utilization
  • Timing analysis of PHYLite Dynamic Reconfiguration
    • APIs for users to tweak PHYlite dynamic configurations
  • Enhanced LVDS dynamic phase shift design example usability features
    • Flexible TCL scripts give users live control over phase-locked loop (PLL) clock shifts

Protocol Interfaces:

  • Arria® 10 PCI Express® (PCIe®) IP features new Data Mover (DMA) Enhancements with support up to 256 tags and simplified usability items including a new look-and-feel PCIe IP GUI and PCIe Link Inspector for debugging
  • ADME support added to the 50G /100G Interlaken MegaCore IPs
  • SerialLite III Streaming IP optimizations include greater throughput and lower overhead to enhance chip-to-chip application performance
  • JESD204B support up to 13.5 Gbps for Arria 10 devices

Video and Image Processing:

Digital Signal Processing (DSP):



Device Support

Device support for all Altera and partner IPs can be found on the Find IP page. 

*Video and Image Processing Suite IP is supported only in Standard and Lite Editions

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