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What's New for IP in v14.1 Release

Altera’s Arria® 10 FPGAs and SoCs are the industry’s only FPGAs available today that support DDR4 memory at these data rates, delivering a 43 percent improvement in memory performance over previous generation FPGAs and a 10 percent improvement in memory performance over competing 20 nm FPGAs. See Arria 10 DDR4 memory interfaces operating at an industry-leading 2,666 Mbps in the following video:

 

10G Ethernet MAC

 

40G/100G Ethernet

 

Interlaken

 

Interlaken Look-Aside  

 

PCI Express

 

DDR4 Memory

 

 

 

Altera delivers all intellectual property (IP) as MegaCore® IPs that are built into the Quartus® II software. The portfolio includes IP for protocol and memory interfaces, digital signal processing (DSP), embedded processors, and related peripherals. The MegaCore IP Library is included in Quartus II Web Edition and Quartus II Subscription Edition.

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New Additions and Enhancements

The v14.1 release of Altera® intellectual property (IP) features new additions and feature enhancements to the MegaCore function portfolio.

Digital Signal Processing (DSP):

Embedded

External Memory Interfaces:

  • All QDR support for Arria® 10 FPGAs now available to be licensed via the QDR Suite
  • DDR3/4 RDIMM and LDRIMM - compilation only
    • Includes simulation support for DDR4 RDIMM
  • Simulation, compilation, and timing closure for the following protocols:
    • DDR3/4 Ping Pong PHY
    • QDR IV
    • X4 DQ/DQS
      • Two DQ/DQS sets per I/O lane
    • 3 V I/O bank support for memory interfaces

Protocol Interfaces:

Video and Image Processing:

The product page for each Altera IP core details its features and benefits including release-specific enhancements.

Device Support

IP support for all device families, can be found on the Find IP page. This page provides device support information for Altera IP and Altera partner IP.

Device Support Levels

IP core device support levels are generally the same as the level of device support provided by Quartus® II software. Table 1 below defines the support levels and Table 2 indicates the current status. Note that only those devices that did not have final device support in the previous software v14.0 release are listed in the table below. Any exceptions for the software v14.1 release where the IP core device support does not match the Quartus II software device support will be indicated in the MegaCore IP Library Release Notes and Errata (PDF).

Table 1. Altera IP Core Device Support Levels

FPGA Device Families
Preliminary Support
The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
Final Support
The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 2. IP Core Device Support Levels

Device Family IP Support
Arria 10 Preliminary
MAX® 10 Preliminary
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