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The v16.0 release of Quartus® Prime design software features new additions and feature enhancements to the MegaCore® intellectual property (IP) portfolio. Click on the images below to learn about some of the exciting new features. For more information and a complete list of feature enhancements, visit our What's New in IP web page.

Best-in-Class PCI Express® IP Performance Demonstration on Arria® 10 300G Interlaken Look-Aside IP Performance Interop with TE Connectivity using Arria 10

JESD204B IP Quick Start Video




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Interlaken Look-Aside 

Altera delivers all intellectual property (IP) as MegaCore® IPs that are built into the Quartus® Prime software. The portfolio includes IP for protocol and memory interfaces, digital signal processing (DSP), embedded processors, and related peripherals. The MegaCore IP Library is included in Quartus Prime Lite Edition, Quartus Prime Standard Edition and Quartus Prime Pro Edition. 

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New Feature Additions and Enhancements

The v16.0 release of Quartus Prime design software features new additions and feature enhancements to the MegaCore IP portfolio. 

All MegaCore IPs can be used in Pro, Standard, and Lite Editions of Quartus Prime software. The product page for each Altera IP core details its features and benefits including release-specific enhancements. For more details on Quartus Prime design software updates, visit the What's New in Quartus Prime page.

Push-button Hardware
Design Examples in Quartus Prime

More Out-of-the-Box Design Examples

More MegaCore IPs now support the new dynamically-generated and configurable hardware design example feature.  This feature was first introduced with our v15.1 release and is enabled in the parameter editor GUI for each core.  The second wave of MegaCore IP supporting this feature include:

Check out the "Push-button Hardware Design Examples in Quartus Prime" video above to see how these design examples provide an out-of-the-box hardware verification platform.

1st Level SignalTap II IP Debug Video

Additional IP Usability Improvements:

External Memory Interfaces:

  • New Arria 10 hardware-verified MegaCore IP:
    • DDR3 RDIMM
    • RLDRAM3 – now supporting 1,200 MHz
  • Improved debug and diagnostics in the EMIF Debug Toolkit featuring:
    • Integration of Traffic Generator 2.0, including control of pseudo-random binary sequence (PRBS) or fixed patterns, in EMIF Debug Toolkit
    • Improvement to Traffic Generator 2.0 for Arria 10 designs – now supports all protocols
  • Hybrid Memory Cube Controller (HMCC) features new Multi Transaction All Packet Size (MTAPS) - resulting in full bandwidth support for smaller payload sizes (< 128B)

Protocol Interfaces:

Video Connectivity and Image Processing:


Digital Signal Processing:

  • LDPC FEC IP MegaCore offers variable code-word length for Wimedia 1.5 and CCSDS compliant NASA encoder/decoder
  • BCH FEC IP MegaCore offers better QoR with lagrangian method encoder
  • FIR Compiler II MegaCore function allows bank switching at frame edges for multi bank mode
  • Shipping C simulation models for all digital signal processing (DSP) IP cores except finite impulse response (FIR) filter (MATLAB model)
  • New Random Number Generator megafunction
    • Supports generation of integer or floating-point numbers in normal distribution or Gaussian distribution
    • Enables hardware test-benching framework for BER generation, modem transmit -> receive model and so on
    • DSP Builder Advanced Blockset design example available (See What's New in DSP Builder)




Device Support

Device support for all Altera and partner IPs can be found on the Find IP page.