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What's New for IP in v15.0 Release

The v15.0 release of Altera® intellectual property (IP) features new additions and feature enhancements to the MegaCore® function portfolio. Some highlights include:

  • Introducing the Hybrid Memory Cube (HMC) MegaCore providing the highest performances for emerging, rapidly increasing memory bandwidth applications.
  • New Arria® 10 FPGA hardware programming support and full Cyclone® V device support for JESD204B MegaCore.
  • New HDMI 2.0 MegaCore released providing multirate support for Arria V, Stratix® V, and Arria 10 FPGAs.

For more information, visit our What's New in IP webpage.

Altera delivers all intellectual property (IP) as MegaCore® IPs that are built into the Quartus® II software. The portfolio includes IP for protocol and memory interfaces, digital signal processing (DSP), embedded processors, and related peripherals. The MegaCore IP Library is included in Quartus II Web Edition and Quartus II Subscription Edition.

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New Additions and Enhancements

The v15.0 release of Altera® intellectual property (IP) features new additions and feature enhancements to the MegaCore® function portfolio.

Digital Signal Processing (DSP):

Embedded

External Memory Interfaces:

  • Introducing the Hybrid Memory Cube (HMC) MegaCore providing the highest performances for emerging, rapidly increasing memory bandwidth applications.
  • Hardware-verified support for DDR3/4 features in Arria® 10 device:
    • PHY-only, error correction code (ECC), 144 bit, multirank (dual-rank, quad-rank)
    • Ping-Pong PHY
    • X4 DQ/DQS
    • DDR4 RDIMM
    • EMIF Debug Toolkit and On-chip EMIF Debug Toolkit
  • Hardware-verified support for QDR IV up to 800 MHz
  • DDR3/3L, DDR2, LPDDR2 hardware support in MAX® 10 FPGAs
  • Power saving enhancement in MAX 10 FPGAs
    • During self refresh, tri-state A/C pins and disable all DDR input buffers except CKE and RESET

Protocol Interfaces:

  • 10GBase-KR Ethernet hardware programming support for Arria 10 FPGAs
  • 40GBase-KR4 Ethernet hardware programing support for Arria 10 FPGAs
  • New Triple-speed Ethernet with 1588 v2 reference design using Linux PTP software stack targeting Arria V SX FPGAs
  • PCI Express® IP continues to reach higher throughput performance levels on 28 nm and 20 nm devices
  • New Altera Debug Master Endpoint (ADME) test and debug feature added to the PCI Express IP
  • New Invalid Bytes Indicator feature on the SerialLite III Streaming IP provides enhanced tracking capability of invalid bytes within a burst of data  
  • New Arria 10 FPGA hardware programming support and full Cyclone® V device support for JESD204B MegaCore function

Video and Image Processing:

  • New HDMI 2.0 MegaCore released providing multi-rate support for Arria V, Stratix® V, and Arria 10 FPGAs
  • The DisplayPort MegaCore now supports Arria 10 FPGAs.  Significant updates have also been made to the design examples for Cyclone V, Arria V, and Stratix V FPGAs
  • We now offer 3G serial digital interface (SDI) support as well as multirate support up to 12G for the SDI II MegaCore for Arria 10 FPGAs

The product page for each Altera IP core details its features and benefits including release-specific enhancements.

Device Support

Device support for all Altera and partner IP can be found on the Find IP page. 

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