Stratix 10 SoC: Highest Performance and Most Power Efficient Processing

Stratix® 10 SoCs are Intel’s (formerly Altera) industry-leading, third-generation SoC FPGA family.  Stratix 10 SoCs, manufactured on Intel’s 14 nm process technology, combine a quad-core ARM® Cortex®-A53 MPCore hard processor system with the revolutionary HyperFlex™ core fabric architecture  to create the highest performance and power efficient SoC FPGA in the industry.

The Stratix 10 SoCs HPS architecture now includes a System Memory Management Unit, which enables hardware virtualization across the processor and FPGA domains.  Stratix 10 SoCs add a Cache Coherency Unit to provide one-way (I/O) cache coherency with the Cortex-A53 MPCore.  Stratix 10 SoCs also include up to 10 TFLOPS of hardened floating-point digital signal processing (DSP) blocks, embedded high-speed transceivers, hard memory controllers, and protocol intellectual property (IP) controllers - all in a single, highly integrated package.

SoC Feature Comparison

Feature Arria V SoC Arria 10 SoC Stratix 10 SoC
Process Technology 28 nm TSMC 20 nm TSMC 14 nm Intel Tri-Gate
Processor Dual-core ARM Cortex-A9 MPCore Dual-core ARM Cortex-A9 MPCore Quad-core ARM Cortex-A53 MP Core
Maximum Processor Performance 1.05 GHz 1.5 GHz 1.5 GHz
Logic Core Performance 300 MHz ~500 MHz 1 GHz
Power Dissipation 1X 0.6X 0.3X
Logic Density Range 350 – 462K logic element (LE) 160 – 660K LE 500K LE - 5.5M LE
Embedded Memory 23 Mb 39 Mb 229 Mb
18 x 19 Multipliers 2,136 3,356 11,520
Maximum Transceivers 30 48  144
Maximum Transceiver Data Rate (Chip to Chip) 10 Gbps 17.4 Gbps 30 Gbps
Memory Devices Supported  DDR3 SDRAM @ 533 MHz

DDR4 SDRAM @ 1,200 MHz

DDR3 SDRAM @ 1066 MHz

LPDDR3 @ 800 MHz
RLDRAM 3 @ 1200 MHz

QDR IV SRAM @ 1066 MHz 

QDR II+ SRAM @ 633 MHz

Hybrid Memory Cube

DDR4 SDRAM @ 1,333 MHz

DDR3 SDRAM @ 1066 MHz
LPDDR3 @ 800 MHz
RLDRAM 3 @ 1200 MHz

QDR IV SRAM @ 1066 MHz

QDR II+ SRAM @ 633 MHz

Hybrid Memory Cube
Hard Protocol IP 2 EMACs
PCI Express® (PCIe®) Gen2 x8
 

3 EMACs
PCI Express Gen3 X 8
10/40G BaseKR- forward error correction (FEC)
Interlaken physical coding sublayer (PCS)
 

 3 EMACs
PCI Express Gen3 X 8
10/40G BaseKR- forward error correction (FEC)
Interlaken physical coding sublayer (PCS)
Security Advanced Encryption Standard (AES)

AES encryption

Authentication based on Elliptic Curve Digital Signature Algorithm (ECDSA), Public key infrastructure with layered hierarchy for root of trust,

Anti-tamper enhancements

AES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF),

ECDSA 256/384 boot code authentication,

multi-factor key infrastructure with layered hierarchy for root of trust,

side channel attack protection

Achieve Performance Breakthroughs with Industry’s Highest Performance FPGAs and SoCs

Break Through the Bandwidth Barrier

  • Up to 144 transceivers with data rates up to 30 Gbps deliver 4X serial transceiver bandwidth from previous generation FPGAs for high port count designs
    • 30 Gbps backplane capability for versatile data switching applications
    • A path to 56 Gbps chip-to-chip/module capability for leading-edge interface standards
  • Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
  • Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 at 2666 Mbps

Lower Operating Expense

  • Quad-core ARM Cortex-A53 processor optimized for performance per watt
  • Leveraging Intel's leadership in process technology, Stratix 10 devices offer the most power-efficient technologies
    • Up to 70% lower power than prior-generation high-end  SoCs
    • Up to 80 GFLOPS/Watt of single-precision floating point power efficiency

Achieve the Highest Level of System Integration

  • 64-bit quad-core ARM Cortex-A53 to enable hardware virtualization, system management and monitoring capabilities, acceleration pre-processing, and more
  • Highest density FPGA fabric with 5.5M logic elements in a monolithic implementation
  • Heterogeneous 3D SiP solutions including transceivers and other advanced components

Obtain the most comprehensive high-performance FPGA security capabilities

  • Integrated Secure Device Manager (SDM) for flexibility to update configuration code
  • Multi-factor authentication
  • Physically Unclonable Function (PUF)

Get Faster Time-to-Market

  • Start design with Arria 10 SoC and migrate to Stratix 10 SoC
    • Code compatability with previous generation SoCs
    • Cortex-A53 supports operating in 32-bit execution mode
  • Complementary Enpirion PowerSoCs offer complete and validated power solution for Stratix 10 SoCs higher performance, lower system power, higher reliability, smaller footprint, and faster time-to-market to power Stratix 10 SoCs

Achieve high designer productivity with optimized FPGA and SoC Design Software

  • Heterogeneous debug, profiling, and whole chip visualization with Intel FPGA SoC EDS featuring ARM Development Suite™ (DS-5™) Altera Edition Toolkit
  • New Spectra-Q™ engine optimized for mulit-million LE FPGA designs providing
    • Up to 8X faster compile times
    • Significant reduction in design iterations
    • Hyper-Aware design flow to optimize designs for HyperFlex architecture
  • C-based design entry using the Intel FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs
  • Heterogeneous C-based modeling and hardware design with Intel FPGA SDK for OpenCL

Stratix 10 SoCs: Designed for Productivity

Design productivity is one of the driving philosophies of the Stratix 10 SoC architecture. Stratix 10 SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of ARM software and tools, and the enhanced FPGA and DSP hardware design flow.

  • Extensive ecosystem of ARM for software development
  • Software compatibility between 28 nm Cyclone® V and Arria® V SoCs and 20 nm Arria  10 SoCs
  • Quartus® Prime software FPGA design suite featuring:
    • High-level automated design flow with Open Computing Language (OpenCL™) compiler
    • Model-based DSP hardware design with DSP Builder for Intel FPGAs
  • Stratix 10 SoC Virtual Platform to enable early software development and verification
Family Overview Table
Family Overview Table
Listing of all Device Variations

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