Intel® Stratix® 10 SoC: Highest Performance and Most Power-Efficient Processing

Intel® Stratix® 10 SoCs, manufactured on Intel’s 14 nm process technology, combine a quad-core ARM* Cortex*-A53 MPCore* hard processor system with the revolutionary Intel® HyperFlex™ FPGA Architecture to deliver breakthrough advantages in performance, power efficiency, density, and system integration. Intel Stratix 10 devices deliver 2X core performance gains over previous-generation, high-performance FPGAs with up to 70% lower power.†

The Intel® Stratix® 10 SoCs HPS architecture now includes a System Memory Management Unit, which enables hardware virtualization across the processor and FPGA domains. Intel® Stratix® 10 SoCs add a Cache Coherency Unit to provide one-way (I/O) cache coherency with the Cortex*-A53 MPCore* processor. Intel® Stratix® 10 SoCs also include up to 10 TFLOPS of hardened floating-point digital signal processing (DSP) blocks, embedded high-speed transceivers, hard memory controllers, and protocol intellectual property (IP) controllers - all in a single, highly integrated package.

By integrating the FPGA and the ARM* processor, Intel® Stratix® 10 SoCs provide an ideal solution for 5G wireless communication, software defined radios, secure computing for military applications, network function virtualization (NFV), and data center acceleration.

Intel® Stratix® 10 Device Demo Videos

28G Transceivers

In this video, we look at the unique transceiver architecture of Intel® Stratix® 10 FPGAs. See H-Tile transceivers that are connected via Intel's EMIB technology and operating at 28 Gbps backplane performance.

Intel® HyperFlex™ FPGA Architecture

Intel® HyperFlex™ FPGA Architecture in Intel® Stratix® 10 devices provides 2X the fMAX performance. This video shows a side-by-side comparison of an original design and a Hyper-Optimized design.



Intel® Stratix® 10 devices, which include PCI Express* (PCIe*) and memory controller hard intellectual property (IP) blocks, combined with Avalon® Memory Mapped and direct memory access (DMA) functions to create a high-performance reference design.

Achieve Performance Breakthroughs 

Break Through the Bandwidth Barrier

  • Up to 144 transceivers with data rates up to 30 Gbps deliver 4X serial transceiver bandwidth from previous generation FPGAs for high port count designs
    • 30 Gbps backplane capability for versatile data switching applications
    • A path to 56 Gbps chip-to-chip/module capability for leading-edge interface standards
  • Over 2.5 Tbps bandwidth for serial memory with support for Hybrid Memory Cube
  • Over 2.3 Tbps bandwidth for parallel memory interfaces with support for DDR4 SDRAM at 2,666 Mbps

Lower Operating Expense

  • Quad-core ARM C*ortex*-A53 processor optimized for performance per watt
  • Leveraging Intel's leadership in process technology, Intel® Stratix® 10 devices offer the most power-efficient technologies
    • Up to 70% lower power than prior-generation high-end  SoCs
    • Up to 80 GFLOPS/Watt of single-precision floating point power efficiency

Achieve High Levels of System Integration

  • 64-bit quad-core ARM Cortex-A53 processor to enable hardware virtualization, system management and monitoring capabilities, acceleration pre-processing, and more
  • Highest density FPGA fabric with 5.5M logic elements in a monolithic implementation
  • Heterogeneous 3D SiP solutions including transceivers and other advanced components

Obtain comprehensive high-performance FPGA security capabilities

  • Integrated Secure Device Manager (SDM) for flexibility to update configuration code
  • Multi-factor authentication
  • Physically Unclonable Function (PUF)

Get Faster Time to Market

  • Start designing with Intel® Arria® 10 SoC and migrate to Intel® Stratix® 10 SoC
    • Code compatability with previous generation SoCs
    • Cortex-A53 processor supports 32-bit execution mode
  • Complementary Intel® Enpirion® PowerSoCs offer complete and validated power solution for Intel® Stratix® 10 SoCs with higher performance, lower system power, higher reliability, smaller footprint, and faster time to market

Achieve high designer productivity with optimized FPGA and SoC design software

  • Heterogeneous debug, profiling, and whole chip visualization with Intel® FPGA SoC FPGA Embedded Development Suite (EDS) featuring the ARM* Development Studio 5* (DS-5*) Intel® SoC FPGA Edition Toolkit
  • New engine optimized for multi-million logic elements (LE) FPGA designs providing
    • Up to 8X faster compile times
    • Significant reduction in design iterations
    • Hyper-Aware design flow to optimize designs for the Intel® HyperFlex™ FPGA Architecture
  • C-based design entry using the Intel® FPGA SDK for OpenCL™, offering a design environment that is easy to implement on SoC FPGAs
  • Heterogeneous C-based modeling and hardware design with the Intel® FPGA SDK for OpenCL™

Intel® Stratix® 10 SoCs: Designed for Productivity

Design productivity is one of the driving philosophies of the Intel® Stratix® 10 SoC architecture. Intel® Stratix® 10 SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of ARM* software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.

  • Extensive ecosystem of ARM for software development
  • Software compatibility between 28 nm Cyclone® V and Arria® V SoCs and 20 nm Intel® Arria® 10 SoCs
  • Intel® Quartus® Prime software featuring:
    • High-level automated design flow with Open Computing Language (OpenCL™) compiler
    • Model-based DSP hardware design with the DSP Builder for Intel® FPGAs
  • Intel® Stratix® 10 SoC Virtual Platform to enable early software development and verification

Family Overview Table

Listing of all Device Variations

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. 

†Comparison based on Stratix V vs. Stratix 10 using Quartus Prime Pro 16.1 Early Beta.  Stratix V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Stratix 10 architecture enhancements of distributed registers in core fabric.  Designs were analyzed using Quartus Prime Pro Fast Forward Compile performance exploration tool.  For more details, refer to HyperFlex FPGA Architecture Overview White Paper:  Actual performance users will achieve varies based on level of design optimization applied.  Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit