Nand Flash Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10

Stratix Series: Stratix IV, Stratix V

Overview

NAND Flash memories are attractive due to their very high density and low price. However, when compared to NOR Flash Memories, they are challenging because they are not fault-free (they need ECC Correction, Bad Block management, etc …) and they are organized like disk drives, with atomic transfers being a whole “page” (no random read/write with data integrity). As a consequence, they cannot be used as straight replacement for NOR Flash memories : they require a specific Controller. At A.L.S.E, we have applied our very strong experience in Memory Controllers and we have developed an extremely compact and efficient -yet low-cost- ONFI SLC NAND Flash Memory Controller with Error Check and Correct. In spite of the compact size, the transfer performance achieved is extremely high (thanks to the embedded and autonomous DMA engine). However, this IP remains simple to use, thanks to its standard Interfaces and its Automatic and Transparent ECC scheme (based on BCH algorithm).

Features

  • High-Performance Controller, with support of NAND Flash Asynchronous Timing Mode from 0 (slowest) to 5 (fastest).
  • Supports 2KB, or 4KB or 8KB NAND page size, and latest NAND memory densities : 32Gbits, 64Gbits, 128Gbits, etc… Supports multiple Dies (CE#)
  • Automatic & Transparent Error Check and Correct. The ECC is based on BCH algorithm, 8 bits correction for 540 bytes of Data.
  • Easy integration with reference designs provided
  • Ability to control the NAND Flash with or without the use of the RDY/BUSY NAND Flash pin.

Device Utilization and Performance

With ECC BCH enabled (8bits correction), the area is typically around 4,000 Logic Elements, and 10 to 20 memory blocks (M9K) are used (depending the NAND Page Size). With ECC Hamming (1bit correction) enabled, the area is typically less than 1,500 Logic Elements, and 4 to 10 memory blocks are used. Runs at miore than 140MHz on a low-cost Cyclone III / IV - CV

Getting Started

Demos are available on existing boards, including AVDB / Clovis ! Contact A.L.S.E

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
QIP File for Easy Integration
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-based driver
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name AVDB / Clovis and many others
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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