10G TCP Offload Engine

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Basic Functions: Miscellaneous

Arria Series: Arria 10, Arria 10 SoC

Stratix Series: Stratix V

Overview

The Algo-Logic Systems' TCP Endpoint implements a full TCP functionality in FPGA hardware which is capable of opening, maintaining, and closing TCP Connections. It has an ultra low latency of 76nanoseconds. The network-tested Algo-Logic TCP Endpoint delivers ultra-high performance and highest TCP bandwidth. It supports full duplex rates of 20 Gbps scalable to 140 Gbps by using multiple ports within a single FPGA. It runs at the full Ethernet clock speed of 156.25 MHz enabling the core to run synchronously with the MAC and application specific processing logic. The implementation is widely deployed on FPGA platforms including Terasic DE5Net, Nallatech P385, Solarflare AOE, and other platforms.

Features

    Device Utilization and Performance

    For 32 Sessions and 128KB retransmission buffer memory, device utilization on Stratix V A7 is: 1. Total registers: 7856 2. Logic utilization: 6580 ALMs (2.81%) 3. Block memory bits: 4286816 (8.17%)

    Getting Started

    Please visit http://algo-logic.com/tcp for more information or contact solutions@algo-logic.com

    IP Quality Metrics

    Basic
    Year IP was first released2013
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportNo CPU needed
    Implementation
    User InterfaceAXI; Other: Avalon ST
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim
    Hardware validated Y. Altera Board Name Terasic DE5-Net, Nallatech P385
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?iperf
    If yes, on which Altera device(s)?Stratix V A7
    If Yes, date performed
    07/14/2014
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  N

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