Supported Device Family:
The Algo-Logic Systems' TCP Endpoint implements a full TCP functionality in FPGA hardware which is capable of opening, maintaining, and closing TCP Connections. It has an ultra low latency of 76nanoseconds. The network-tested Algo-Logic TCP Endpoint delivers ultra-high performance and highest TCP bandwidth. It supports full duplex rates of 20 Gbps scalable to 140 Gbps by using multiple ports within a single FPGA. It runs at the full Ethernet clock speed of 156.25 MHz enabling the core to run synchronously with the MAC and application specific processing logic. The implementation is widely deployed on FPGA platforms including Terasic DE5Net, Nallatech P385, Solarflare AOE, and other platforms.
- 76 ns ultra low latency with available sessions per instance: 32, 64, 128, 256, 512, 4K, and 16K.
- Programmable TCP retransmission buffer and fast retransmit option.
- Layer 1: IEEE802.3; layer 2: IEEE802.3, ARP, VLAN; layer 3: IPv4 and ICMP; layer 4: TCP, UDP.
- Robust flow control and error control.
- TCP option support: MSS, window scaling, timestamps.
IP Quality Metrics
|Year IP was first released||2013|
|Latest version of Quartus supported||15.1|
|Altera Customer Use|
|IP has been successfully implemented in production with at least one customer||Y|
Customer deliverables include the following:
|Parameterization GUI allowing end user to configure IP||N|
|IP core is enabled for OpenCore Plus Support||N|
|Software drivers provided||N|
|Driver OS support||No CPU needed|
|User Interface||AXI; Other: Avalon ST|
|IP-XACT Metadata included||N|
|Hardware validated||Y. Altera Board Name Terasic DE5-Net, Nallatech P385|
|Industry standard compliance testing performed||Y|
|If yes, which test(s)?||iperf|
|If yes, on which Altera device(s)?||Stratix V A7|
|If Yes, date performed||07/14/2014|
|IP has undergone interoperability testing||Y|
|Interoperability reports available||N|
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