H264-E-BPF - Ultra-fast, 4k-Capable, AVC/H.264 Baseline Profile Encoder

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone V

Stratix Series: Stratix IV, Stratix V

Overview

This video encoder supports the Constrained Baseline Profile of the H.264 standard It implements an ultra-high throughput, UHD- capable hardware encoder that is optimized for ultra-low-latency video streaming at low bit rates. The H264-E-BPF requires significantly less silicon area than most equally capable H.264 cores allowing for cost-effective FPGA implementations. Its small silicon footprint, low memory bandwidth, and zero software overhead enable H.264 coding at an extremely low energy cost. Depending on its configuration the core is able to process Full-HD or UHD/4K video on Altera FPGAs. The core produces high quality video, even at low bit-rates, and features extremely low latency. It uses a constant Qp to output VBR streams, or automatically regulates Qp to output CBR streams. In CBR mode it responds rapidly to video content changes. This can be combined with Intra-Refresh coding to effectively eliminate bit-rate peaks, while preserving the periodic intra-coded references.

Features

    Device Utilization and Performance

    The core can be mapped to any Altera Family (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. When configured to process 1 pixel every 2 clock cycles (H264-E-BPf/2) the core synthesizes to 20k ALMs, 816k Memory bits, and 18 DSP blocks. Under this configuration, It can process 720p60, 1080p50 on several Altera FPGA devices. When configured to process 1 pixel every clock cycle (H264-E-BPf/1) the core synthesizes to 38k ALMs, 1.1M Memory bits, and 36 DSP blocks. Under this configuration, It can process 1080p60, or UHD/4k at 25 or 30fps on several Altera FPGA devices.

    Getting Started

    Contact CAST at info@cast-inc.com to arrange for a core evaluation

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportN/A
    Implementation
    User InterfaceAXI; Other: Simple native interface
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelsim, Questa, NCSIM
    Hardware validated Y. Altera Board Name DK-DEV-4SGX230N & DK-START-5AGXB3N
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

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