CCSDS LDPC Decoder IP

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Creonic CCSDS LDPC IP support the LDPC coding scheme as defined by the CCSDS standard. The LDPC code with single rate 223/255 was specially designed for Near-Earth missions, but the excellent error correction performance makes it the ideal fit for further high-throughput applications. The IP cores are available for ASIC and FPGAs (Altera).

Features

  • -support for code rate 223/255 (7136/8160)
  • -coded block size 8160 bits
  • -compliant with "TM Synchronization and channel coding

Device Utilization and Performance

-1.6 Gbit/s coded throughput at 200 MHz -decoding latency of 4.3 µs at 5 layered decoder iterations and 200 MHz -encoding latency of 40ns at 200 MHz

Getting Started

Please contact Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name SLS Cyclone III based CoreCommander, SLS Embedded System Development Kit (ESDK)
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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