DMA Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Basic Functions: DMA

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The DMA controller is designed for data transfer in different system environments. Two module types : type 0 and type 1 are provided, and the user can choose the number of each module type. Type 0 modules are designed to transfer data residing on the same bus, and Type 1 modules are designed to transfer data between two different buses. Each module can support up to 4 DMA channels and the IP supports up to 16 total DMA channels. Each DMA channel can be programmed for various features, such as transfer size, synchronized and unsynchronized transfer control, transfer priority, interrupt generation, memory and I/O address space, and address change direction. This IP is designed to work with 32-bit and 64-bit bus systems, including the PCI bus, PowerPC bus, and other CPU host buses. It can also be integrated with other IP to form a complete functional block.

Features

    Device Utilization and Performance

    2300 LE

    Getting Started

    For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

    IP Quality Metrics

    Basic
    Year IP was first released2000
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedN
    Driver OS supportOS independent
    Implementation
    User InterfaceAXI; Other: Generic/Wishbone/PLB
    IP-XACT Metadata includedN
    Verification
    Simulators supportedVerilog/VHDL
    Hardware validated Y. Altera Board Name Custom build board
    Industry standard compliance testing performed
    N
    If No, is it planned?N
    Interoperability
    IP has undergone interoperability testing
    N
    Interoperability reports available  N

    Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.