PCI Bus Arbiter

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: PCI

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master. The PCI bus arbiter implements either rotating priority or a fixed priority scheme. In the rotating priority scheme, the requestor that is most recently granted the bus receives the lowest priority, while the requestor position next to it receives the highest priority. The remaining requestor receives subsequently lower priority based on its position. This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.

Features

  • Complies with PCI bus specification 2.2
  • Designed for programmable logic device (PLD) and ASIC implementation in various system environments
  • Fully static design with edge-triggered flip-flops
  • Supports two to any number of bus masters

Device Utilization and Performance

239 LE

Getting Started

For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

IP Quality Metrics

Basic
Year IP was first released2000
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS supportAll PCI compatible
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
IP-XACT Metadata includedN
Verification
Simulators supportedVerilog/VHDL
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
Y
If yes, which test(s)?PCI Compliance
If yes, on which Altera device(s)?Flex10K
If Yes, date performed
01/01/1997
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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