SD 3.0/eMMC 4.5 Host Controller (EP553)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus, Source Code

Technology: Processors and Peripherals: Peripherals

Arria Series: Arria 10, Arria V, Arria 10 SoC, Arria V SoC

Cyclone Series: Cyclone IV, Cyclone V, Cyclone V SoC

MAX Series: MAX 10, MAX V

Stratix Series: Stratix IV, Stratix V

Overview

The EP553 SD/eMMC host controller connects the host CPU to the system’s SD card socket to allow it to access SD/MMC cards. It supports SD 3.0, SDXC, SDHC, SDIO, SD Combo and eMMC cards. The SD host controller core is compliant to the latest SD 3.0 host specification. It supports all the latest features including double data rate transfer UHS-I speed modes and a wide choice of user interface buses. To access SD card, the host CPU simply access the control registers inside the core. The core handles all the SD card protocol automatically including data shifting, timing and CRC. The core has built-in DMA controller so that data can be automatically transferred between system memory and the SD card without CPU intervention. The EP553 is recognized by any operating systems that supports the SD bus. No driver development is needed. Eureka also provides free source code to users who develop their own software.

Features

    Device Utilization and Performance

    2200 LE, 4 RAM block, 100 Mhz

    Getting Started

    For additional information, contact Eureka Technology, Inc. at: Tel. (650) 960-3800 Email: info@eurekatech.com WWW: http://www.eurekatech.com

    IP Quality Metrics

    Basic
    Year IP was first released2004
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Y
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Verilog; VHDL
    Testbench languageVerilog; VHDL
    Software drivers providedY
    Driver OS supportOS independent
    Implementation
    User InterfaceAXI; Avalon-MM; Other: Generic/Wishbone/PLB
    IP-XACT Metadata includedN
    Verification
    Simulators supportedVerilog/VHDL
    Hardware validated Y. Altera Board Name Custom build board
    Industry standard compliance testing performed
    Y
    If yes, which test(s)?SD Specification
    If yes, on which Altera device(s)?Cyclone
    If Yes, date performed
    01/01/2004
    Interoperability
    IP has undergone interoperability testing
    Y
    Interoperability reports available  Y

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