Designing for high performance serial transceiver applications using series 10 ALTERA FPGAs Arria 10 GX 660/1150 KLEs Hardware, software design tools, IP, and pre-verified reference designs Loopback boards, cables, and extension IOs board are available in the kit content PCIe with 8 lanes at 8 Gb/s link rate (Gen3) Advanced memory interface with DDR4 SODIMM memory up to 16 GB, support ECC and Non ECC Enabling serial connectivity with QSFP+ with 4 XCVR links: 12.5 Gb/s per link* Develop networking applications with RJ45 copper connector 10/100/1000 Base-T Ethernet (Through RGMII PHY) Implement Video display applications with Display output port Rev 1.2 (up to 5.4Gbit/s) Expand I/O connector with 2 connectors in order to improve a front end of 32 high speed link. On board programmable PLL oscillator (Si5341), highly flexible and configurable clock generator/buffer. The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front end The FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only (+vadj) •160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V) •4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS •10 XCVR (up to: 12.5 Gb/s)* * Production Device with transceiver speed grade 4 can reach 12.5 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s
- Board Support Package (BSP)
- OpenCL HPC BSP (upon request)
Board Quality Metrics
|Latest version of Quartus supported||15.1|
|Required Collateral Available|
|Reliability / Quality Assurance|
Defects per Million Opportunities (DPMO)
|Parts per Million (PPM)
|Return Material Authorization (RMA) Policy||Available on request through REFLEX CES support web site.|
|CE Compliant||Y. Yes|
|Conflict Mineral Policy Compliant
|Test Plan Summary|
ReFLEX CES provides all the files required to enable and test interfaces or help the user to start his own design.
|ISO 9000 & 9001|
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