DSP 1080p HD Video

Intel developed a video design framework that enables the fastest design cycle for video application. The components of this framework are as follows:

  • A library of basic building blocks of video and image processing (VIP) intellectual property (IP) cores designed for easy plug-and-play type interface
  • A low-overhead streaming video interface protocol, which is available as an open standard
  • System integration tools such as the Platform Designer (formerly Qsys) that provide an automated way of generating control and arbitration logic
  • A suite of high definition (HD) reference designs that can be used as a starting point for your video datapath designs

The Avalon® Streaming (Avalon-ST) interface video protocol is designed for sending video and control data from one video processing block to the other.

This protocol is open and you can freely download the specification via the web. Using this specification does not bind you to using Intel FPGAs. However, all the video IP and video reference designs utilize this interface.

Figure 1 shows how different video functions can be connected using this protocol. More information on this protocol is available in the ‘Interface’ section of the Video and Image Processing Suite User Guide (PDF).

Figure 1. Avalon-ST Protocol for Video Interfaces and Avalon Memory-Mapped (Avalon-MM) Protocol for Control Plane Interfaces

Figure 2. Avalon Streaming (ST) Protocol for Video Interfaces and  Avalon Memory Mapped (MM) Protocol for Control Plane Interfaces

Video systems almost always include an embedded processor and a memory subsystem to manage the video frames in the external memory. The Platform Designer (formerly Qsys ) greatly simplifies embedded system design. This tool includes a library of components, such as soft core processors (Nios® II embedded processors), Avalon interfaces, memory controllers, bridges, and digital signal processing (DSP) IP cores. It also features a connectivity GUI and generator to automatically wire up arbitrated and streaming bus systems.

Figure 2. Platform Designer Design Flow for Video Datapaths

Finally, the entire video design framework comes together in the form of an HD reference design that showcases the actual video processing common to many applications.