Design Solutions

It’s one thing to understand the architectural solution to a set of design requirements. It’s another thing to see how an FPGA might fit into that architecture. Design Solutions provide examples of how our customers or partners have solved real problems using FPGAs. We hope you’ll find them valuable as a source of design ideas, and as stimulus to your creativity on the many ways FPGAs can play a role in solving today’s most challenging design problems.

Boosting the Speed of Image Searches
By Hidetoshi Matsumura, senior researcher, Fujitsu Laboratories

Fujitsu developed a partial image match algorithm that could identify document pages with sections that appeared similar to the images on a search page. With FPGA acceleration, the algorithm became a practical tool for searching massive document stores.

A 2.5 TFLOPS ATCA Radar Signal Processor
By Richard Jaenicke, Director Market Development, Mercury Systems

Read how Mercury Systems used Xeon sever-class CPUs and Arria 10 FPGAs to build a heterogeneous compute platform for radar signal processing deployed for ship borne and aircraft military systems

Expanding the Applications of Stereo Machine Vision
By Eiji Iwai, Senior Engineer, Embedded Technology Department, Solution Business Division, FUJISOFT

Using new algorithms optimized for small FPGAs, Fujisoft has developed a single-chip stereo vision-processing subsystem than brings stereo vision processing to a wide range of embedded systems.

A Controller Redesign Slashes the Cost of Data-Center Storage
By Pearse Coyle, CEO, NVMdurance

The solution is an analysis tool and a highly-configurable SoC-FPGA-based solid-state storage controller. The controller continuously monitors the condition of the NAND flash during operation and automatically adjusts the controller operating parameters in real time. The controller uses these parameters in managing the NAND array and in conducting individual transactions greatly expanding the useful life of the NAND chips

A Carrier-Grade Ethernet Switch in One SoC

By Alex Kugel, Intel® (Formerly  Altera)

Designers implemented a 5-port, full-duplex Gbit switch that received Metro Ethernet Forum Carrier Ethernet 2.0

certification. There is adequate headroom in both the FPGA fabric and the dual CPU cores for applications to work in conjunction with the switch.

Hardware Acceleration for Map/Reduce Analysis of Streaming Data Using OpenCL
By Jim Costabile, CEO/Founder, Syncopated Engineering Inc.

Map/Reduce has become a fundamental tool of big-data analysis, and the performance of the function directly impacts the response time of systems depending on the analysis, from text search to image recognition. Fortunately, research is showing that map/reduce can be significantly accelerated by FPGAs. This Design Example shows use of OpenCL to develop a map/reduce accelerator that can be easily retargeted for conventional memory-based or for streaming use.

Forging a Single Agile Radio Platform for Signal Intelligence and Public Safety
By Brandon Malatest, COO, Per Vices

Software-defined radio (SDR) promises a lot: the agility to move between frequency bands, modulation schemes, and data formats without changes in hardware. But in reality, such agility has come at the cost of expensive, power-hungry baseband-processor hardware. In this Design Solutions article SDR specialist Per Vices shows how they overcame the challenges of agile baseband processing by employing an FPGA for the most compute-intensive tasks.

Fujisoft solves graphics acceleration for the Android platform
by Hiroyuki Ito, Senior Engineer, Fujisoft

While many embedded-systems design teams are adopting the Android platform, some are running into a critical issue. Android APIs assume a smooth, interactive graphic user interface with metaphors that require a high level of graphic processing. But the microcontrollers generally used in embedded designs do not have that kind of graphics power. In a classic example of employing FPGAs to tame computing hot spots, Fujisoft developed a compact set of graphics engines that accelerated the most difficult functions in the Android graphics system, offloading the CPUs and allowing low-cost embedded Android platforms without sacrifice of the expected user interface.