Designing Digital Down Conversion SystemsUsing CIC and FIR Filters

The Designing Digital Down Conversion Systems design example, featuring the Altera® CIC and FIR MegaCore® functions, demonstrates a multichannel, multirate digital system using Altera's DSP MegaCore intellectual property (IP).

Sample rate conversion has a wide range of applications in modern digital systems, especially wireless communications systems such as WCDMA and WiMAX systems. Efficient implementation of decimation and interpolation can be accomplished by concatenating cascaded-integrator-comb (CIC) and finite impulse response (FIR) filters.

This example demonstrates a data rate down conversion system that can be commonly seen in time division multiplexing (TDM) WiMAX receivers. The overall system diagram is shown in Figure 1. 

Figure 1. TDM Digital Down Conversion System Block Diagram

Model

The input to the design example is from two independent data sources, such as the inphase (I) and quadrature (Q) components of a digital communications system. The inphase signal is a sine wave with a center frequency of 4.57 MHz. The quadrature signal is a cosine wave also centered at 4.57 MHz. The combined, time multiplexed input data stream is sampled at 182.784 MHz, so the corresponding data rate for the inphase and quadrature signals is 91.392 MHz. Part of the input signal is corrupted by high-frequency additive noise.

The CIC and FIR filters convert inphase and quadrature signals sample rate to 11.484 MHz while maintaining the input signals spectrum information. The decimation filters also reject out-of-band noise. Therefore, the output of this rate conversion system should be noiseless down sampled sinusoidal waves of frequency 4.57 MHz. For well defined rate change systems, the narrow band information signal should maintain its spectrum from input to output, as demonstrated in this design example.

Features

  • Decimation or interpolation is implemented efficiently using the Altera CIC Compiler MegaCore function.
  • Altera's FIR Compiler is configured to have an inverse sinc frequency response to compensate CIC filter droop.
  • A MATLAB script designing CIC compensating filter is provided for your reference. The script uses the frequency sampling method to design a FIR filter that has an inverse sinc frequency response. The overall system response is plotted for you to verify key system specifications such as the pass-band ripple and stop-band attenuation.
  • Multiple input data sources are supported. For wireless and wireline applications, input data can be viewed as time division multiplexed. For other applications, data sources can be viewed as interleaved.
  • Altera's Packet Format Converter is included to properly de-interleave multiple data sources for display.
  • Altera's Avalon® Streaming Interface (ST) transfers packet data from multiple data sources between cores. For more information about Avalon-ST, please refer to the Avalon Interface Specifications (PDF).

Files

Download the files used in this example:

 

The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.

Files in the zip download include:

  • TDMDDC.mdl - DSP Builder design file
  • ciccomp.m - MATLAB script for designing an inverse sinc CIC compensation filter
  • cic.vhd - wrapper file to generate the Altera CIC Compiler IP core
  • fir.vhd - wrapper file to generate the Altera FIR Compiler IP core
  • fdcoeffR4N8M1L110.txt - pre-generated compensating FIR filter coefficients

Parameters

CIC and Compensation FIR Design Example in DSP Builder

 

Table 1 shows the overall frequency response specifications. Select parameters for CIC and FIR filters (see Tables 2 and 3) based on the frequency response requirement.

Table 1. WiMAX DDC Example Total Spectrum Requirement

Parameters Value
Input Sampling Frequency91.392 MHz
Output Sampling Frequency11.424 MHz
Pass-Band Edge4.75 MHz
Pass-Band Ripple< 0.05 dB
Stop-Band Attenuation> 90 dB

Table 2. Parameters for CIC Filter

CIC Parameters Value
Filter TypeDecimation
Number of Stages8
Rate Change Factor4
Differential Delay1
Number of Interfaces1
Number of Channels Per Interface2
Input Data Width8
Output Data Width16
Hogenauer PruningOn
Output RoundingConvergent

Table 3. Parameters for FIR Filter

FIR Parameters Value
Rate SpecificationDecimation by 2
Input Channels2
Input BitwidthSigned binary 16
Output BitwidthFull resolution
Coefficient ScalingNone
Device FamilyStratix® II
StructureMCV
Pipeline Level2
Clocks per Output Data2
Data StorageM4K
Coefficient StorageM512
MultiplierDSP blocks
Coefficients InputFrom file

Related Links

 

 

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