Description
If both RP and EP PCIe® devices support Gen2 and the link only comes up in Gen1 speed,
then this may be the setup issue.
Per PCIe base spec, when the link successfully enters L0 in Gen1, software must set bit 5 of Link Control register in the root port to trigger retraining link for Gen2 negotiation.
For Altera® PCIe core, the Link Control register is located at 0x90 in PCI configuration space.