Article ID: 000079907 Content Type: Troubleshooting Last Reviewed: 08/22/2023

Which HPS SDRAM Controller command ports are associated with which AXI interfaces?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Cyclone® V and Arria® V HPS SDRAM controller allows up to 3 AXI™ interfaces.  The following shows the mapping of the SDRAM controller command port to the AXI interface read/write channel. 

    • Command port 0: f2h_sdram0 AXI Read commands
    • Command port 1: f2h_sdram0 AXI Write commands
    • Command port 2: f2h_sdram1 AXI Read commands
    • Command port 3: f2h_sdram1 AXI Write commands
    • Command port 4: f2h_sdram2 AXI Read commands
    • Command port 5: f2h_sdram2 AXI Write commands

     

     

    Resolution

    This information is included starting with release 15.1 of the Arria® V and Cyclone® V Handbook.

     

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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