Description
If the RdDmaWaitRequest_i signal is asserted for an extended period of time, the internal storage of the Read DMA Module becomes full, causing the Hard IP for PCI Express® to receive FIFO to become full. Once the FIFO is full, the processing of incoming packets stops for as long as the RdDmaWaitrequest_i signal is asserted.
Resolution
Redesign your RTL to avoid issuing RdDmaWaitRequest_i. Alternatively, limit its duration to a few clock cycles per transaction.