Why do I see setup time violation on my I/O paths in the Quartus II software version 13.0 SP1?

You may see setup time violations on your I/O paths that use Hard Memory Controller (HMC) pins as I/O pins on Cyclone® V devices in the Quartus® II software version 13.0 SP1. I/O signals that use HMC pins are routed using HMCPHY_RE routing elements have a significantly higher routing delay compared to other pins. These routing delays are part of the Cyclone V timing models in the Quartus II software version 13.0 SP1 and were not included in earlier timing models.

Avoid using HMC DQ pins as the input pin for high-speed signals.

Avoid using HMC DQ  and command pins as the output pin for high-speed signals.

You can refer to HMC Pin column of Cyclone V device pin-out files to identify the HMC pins of your targeted device.