Article ID: 000079061 Content Type: Troubleshooting Last Reviewed: 08/21/2012

Why does my DCFIFO not function correctly in hardware?

Environment

  • Quartus® II Subscription Edition
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 11.1, timing paths to the memory block inside a DCFIFO megafunction may not be analyzed correctly. This problem may result in designs failing in hardware even though the design reports no timing violations. This problem affects designs containing DCFIFO megafunctions that target the following device families:

    • Stratix® series beginning with Stratix II devices
    • Arria® series beginning with Arria GX devices
    • Cyclone® series beginning with Cyclone II devices
    • HardCopy® series beginning with HardCopy II devices

    Even if your design does not instantiate a DCFIFO megafunction directly, it may be included within other IP. To identify whether your design is affected by this problem, search for either of the following messages in your design\'s TimeQuest timing analyzer report file, <revision>.sta.rpt:

    • Info (332166): set_false_path -from * -to *fifo_ram*
    • Info (332166): set_false_path -from * -to *fifo_lutram*

    This problem does not affect earlier versions of the Quartus II software.

    Resolution

    A patch is available to fix this problem for the Quartus II software version 11.1. Download and install patch 0.12 from the appropriate link below. Altera recommends all users of the Quartus II software version 11.1 upgrade to version 11.1 SP1 or download and install patch 0.12. After installing the patch, recompile your design to reflect the corrected timing behavior.

    This problem is fixed beginning with the Quartus II software version 11.1 SP1.

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    This article applies to 31 products

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