Intel® FPGA IP for Ethernet - Support Center

Welcome to the Intel® FPGA Intellectual Property (IP) for Ethernet Support Center!

Here you will find information on how to select, design, and implement Ethernet links. There are also guidelines on how to bring up your system and debug the Ethernet links. This page is organized into categories that align with an Ethernet system design flow from start to finish.  

Enjoy your journey!

Refer to Table 1 to understand the Ethernet intellectual property (IP) core support for Intel® Stratix® 10 and Intel® Arria® 10 devices. Compare between the two devices to select the right device for your Ethernet subsystem implementation.

Table 1 - Device and IP Core Support
Device Family IP Core  Electrical Interface Forward Error Correction 1588 Precision Time Protocol Auto Negotiation/ Link Training
Intel® Cyclone® 10 LP/GX Intel® FPGA IP for Triple Speed Ethernet
View IP core user guide
10BASE-T 100BASET 1000BASE-T 1000BASE-X   check mark check mark

Intel® FPGA IP for Low Latency Ethernet 10G MAC 

(Cyclone 10 GX only)
View IP core user guide

10GBASE-R   check mark  
Intel® Arria® 10 GX/GT/SX Intel® FPGA IP for Triple Speed Ethernet
View IP core user guide
10BASE-T 100BASET 1000BASE-T 1000BASE-X   check mark check mark
Intel® FPGA IP for Low Latency Ethernet 10G MAC
View IP core user guide
View design example user guide
10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T Firecode FEC check mark check mark
Intel® FPGA IP for 10GBASE-R
View IP core user guide
Intel® FPGA IP for XAUI PHY
View IP core user guide
Intel® FPGA IP for 1G/10GbE and 10GBASE-KR PHY
View IP core user guide
Intel® FPGA IP for 1G/2.5G/5G/10G Multi-rate Ethernet PHY
View IP core user guide
Intel® FPGA IP for Low Latency 40 Gbps Ethernet
View IP core user guide
View design example user guide
40G-BASE-R4 Firecode FEC check mark check mark
Intel® FPGA IP for Low Latency 100 Gbps Ethernet
View IP core user guide
View design example user guide
100G-BASE-R10 100G-BASE-R4 Reed Solomon (528, 514) check mark  
Intel® FPGA IP for 25 Gbps Ethernet
View IP core user guide
View design example user guide
25G-BASE-R1 Reed Solomon (528, 514) check mark  
Intel® FPGA IP for 50 Gbps Ethernet
View IP core user guide
View design example user guide
50G-BASE-R2      
Intel® Stratix® 10 GX/SX/MX/TX Intel® FPGA IP for Triple Speed Ethernet
View IP core user guide
10BASE-T 100BASET 1000BASE-T 1000BASE-X   check mark check mark
Intel® FPGA IP for Low Latency Ethernet 10G MAC
View IP core user guide
View design example user guide
10BASE-T 100BASET 1000BASE-T 1000BASE-X 10GBASE-R NBASE-T MGBASE-T Firecode FEC check mark check mark

Intel® FPGA IP for 10GBASE-R
View IP core user guide for L-tile

View IP core user guide for H-tile

Intel® FPGA IP for 10GBASE-KR PHY
View IP core user guide 
Intel® FPGA IP for 1G/2.5G/5G/10G Multi-rate Ethernet PHY
View IP core user guide
Intel® FPGA IP for 25-Gbps Ethernet 25G-BASE-R1 Reed Solomon (528, 514) check mark  
Intel® FPGA IP for Low Latency 40-Gbps Ethernet
View IP core user guide
View design example user guide
40G-BASE-R4 Firecode FEC   check mark

Intel® FPGA H-Tile Hard IP for Ethernet

View IP core user guide
View design example user guide

50G-BASE-R2

100G-BASE-R4

    check mark
Intel® FPGA IP for Low Latency 100-Gbps Ethernet
View IP core user guide
View design example user guide
100G-BASE-R4 Reed Solomon (528, 514)    
Notes:

Please refer to the respective user guides to understand and find out whether the various features listed in the table above are mutually exclusive. For example: Intel® FPGA IP for Low Latency 100 Gbps Ethernet (for Intel® Arria® 10 devices) does not allow you to enable the RS-FEC and 1588 PTP simultaneously.

PHY Interface for Ethernet Using the Transceiver Native PHY IP Core

You can also implement just the physical layer of the Ethernet using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

For more information, refer to the following PHY user guides:

Title Description
How Altera® 1588 System Solution Work in Different Clock Mode Learn about Intel's new 1588 system-level reference design using both the Intel FPGA IP for 10G Ethernet MAC with 10G BaseR PHY and software, which includes the PTP stack LinuxPTPv1.5, a preloader, a 10 Gbps Ethernet MAC driver, and a PTP driver.
Debug Techniques for an Altera® Nios® II Ethernet Design - Part 1 Learn about debugging techniques for Ethernet or Nios® II processor designs.
Debug Techniques for an Altera® Nios® II Ethernet Design - Part 2 Learn about debugging techniques for Ethernet or  Nios® II processor designs.
How to Debug Altera Triple Speed Ethernet Auto Negotiation Issue Learn how to use auto negotiation for synchronizing Ethernet peripherals.
How to Debug TSE Auto-Negotiation Issue Learn how to debug triple-speed Ethernet link synchronization issues.
How to Migrate Intel FPGA Triple Speed Ethernet to Arria® 10 Devices in Quartus® Software Learn how to migrate IP cores to the Intel® Arria® 10 FPGA family using the Intel® FPGA IP for Triple-Speed Ethernet as an example.
Migration from legacy 10G Ethernet MAC IP to the new low latency 10G Ethernet MAC IP Learn about the Intel® FPGA IP for Low Latency 10G Ethernet MAC and how to migrate from the legacy Intel FPGA IP for 10G Ethernet MAC.
Networking Features Under UEFI Shell Learn how to use the Ethernet features under the UEFI Shell after booting to the DXE phase.
Scalable 10G MAC + 1G/10G PHY with 1588 Design Example Hardware Demo Watch a demonstration on the Intel® FPGA IP for 10G Ethernet MAC and the Intel® FPGA IP for 1G/10G PHY with the IEEE 1588 feature. Learn how to perform the design hardware test and how to modify the hardware tcl script to specify the purpose of the test.
Intel 2.5G Ethernet IP Watch the 2.5G Ethernet IP Chalk Talk video

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