Agilex® 5 Device Quick Links

Collection of the device overview, datasheet, and known issues list documents.

Recommended Agilex 5 documents such as the configuration, power management, transceiver user guides, pin connection guidelines and more.

Table view of the Device Family's Resources, Packages and Migration Information vs. Device Densities.

Deepen your expertise with Agilex 5 FPGA training courses.

See all Application Notes, Device Design Guidelines, and Reference Design Overviews.

Provides introductions, feature summaries, and block diagrams for the family.

Provides the electrical specifications for the stated device(s).

Provides information about features and usage of the product, software, and/or IP.

Provides a list of known issues affecting the device or software.

Provides Package Mechanical Drawings, Package Ball Coordinates and other package related information.

Provides the pin description and connection guidelines.

Provides device pin-out information in up to two formats: XLS and PDF.

Provides information about the registers, address blocks, bit information and more for IP blocks.

Provides a summary of new features and enhancements to the software and/or IP.

Provides documentation to plan, design, implement, and verify your external memory interfaces.

Provides information on how to select, design, and implement Ethernet links.

Provides documentation on the HPS system architecture and features.

Provides information about how to select, design, and implement PCIe links.

Optimized for power and size – ideal for intelligent applications at the edge, embedded, and more. Provides transceiver rates up to 17 Gbps and 28 Gbps, a multi-core ARM SoC, and enhanced DSP with AI Tensor Blocks.

Optimized for performance and power efficiency – ideal for various applications across multiple markets. Provides transceiver rates up to 28 Gbps, a multi-core ARM SoC, and enhanced DSP with AI Tensor Blocks.

Provides information on available Dev Kits and their key features from Altera and also our Partners.

Provides designs that can be used as a starting point for developing with your unique system.

Provides documentation on the Intellectual Property (IP) that covers a wide variety of applications with their combination of soft and hardened IP cores along with reference designs for Agilex 5 devices.

Provides documentation on the associated software like Quartus® Prime Pro Edition, Simics® Simulator, FPGA AI Suite and more.

Provides boundary-scan description language (BSDL) files for appropriate device package.

Provides the input/output buffer information specification (IBIS) files for Agilex 5 devices.

Provides the thermal resistance information includes device pin count, package name, and resistance values. You must be signed in with your MyAltera account in order to access the above link. NDA Required.