Agilex® 7 Device Quick Links

Collection of the device overview, datasheet, and known issues list documents.

Recommended Agilex 7 documents such as the configuration, power management, transceiver user guides, pin connection guidelines and more.

Table view of the Device Family's Resources, Tiles, Packages and Migration Information vs. Device Densities.

Deepen your expertise with Agilex 7 FPGA training courses.

See all Application Notes, Device Design Guidelines, and Reference Design Overviews.

Provides introductions, feature summaries, and block diagrams for the family.

Provides the electrical specifications for the stated device(s).

Provides information about features and usage of the product, software, and/or IP.

Provides a list of known issues affecting the device or software.

Includes the ordering code reference, package acronym, materials, and other special information.

Provides the pin description and connection guidelines.

Provides device pin-out information in up to three formats: PDF, XLS, and TXT.

Provides information about the registers, address blocks, bit information and more for IP blocks.

Provides a summary of new features and enhancements to the software and/or IP.

Provides documentation to plan, design, implement, and verify your external memory interfaces.

Provides information on how to select, design, and implement Ethernet links.

Provides documentation on the HPS system architecture and features.

Provides information about how to select, design, and implement PCIe links.

E-tile Technical Documentation filtered view.

P-tile Technical Documentation filtered view.

F-tile Technical Documentation filtered view.

R-tile Technical Documentation filtered view.

Targeted for a wide range of applications, with transceiver rates up to 58 Gbps, advanced DSP blocks and high-performance crypto blocks.

Targeted for bandwidth-intensive applications, with transceiver rates up to 116 Gbps, PCIe 5.0 support, and with Compute Express Link (CXL) support.

Targeted for compute and memory-intensive applications expands upon Agilex® I-Series device features memory enhancements and a hard memory Network-on-Chip (NoC).

See available Dev Kits and their key features.

Provides designs that can be used as a starting point for developing with your unique system.

Provides documentation on the Intellectual Property (IP) that covers a wide variety of applications with their combination of soft and hardened IP cores along with reference designs for Agilex 7 devices.

Provides documentation on the associated software like Quartus® Prime Pro Edition, FPGA SDK for OpenCL™ Pro Edition, DSP Builder and more.

Provides boundary-scan description language (BSDL) files for appropriate device package.

Provides the input/output buffer information specification (IBIS) files for Agilex devices.

Provides the thermal resistance information includes device pin count, package name, and resistance values. You must be signed in with your My account in order to access the above link. NDA Required.