EDA Partners: FPGA EDA Systems
EDA ecosystem ensures that you have a complete design solution in designing, verifying, and integrating FPGAs into your systems.
System-Level Design
| EDA Vendor | Product Name | Design Solution |
|---|---|---|
| Altium | Altium Designer | High-level design tool |
| Agnisys Technology Pvt Ltd | IDesignSpec | Register map management |
| Bluespec | RISC-V Tools | High-level synthesis |
| Cadence Design Systems, Inc. | Stratus High-Level Synthesis | High-level synthesis |
| NEC | CyberWorkBench | High-level synthesis |
| SynaptiCAD | TestBencher Pro | High-level design tool |
Design Creation
Product Name |
Design Solution |
|
|---|---|---|
Project management, design entry, and analysis tool |
||
Design entry, code comprehension, project management, and collaboration |
Synthesis
Product Name |
Design Solution |
|
|---|---|---|
Logic synthesis |
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Advanced logic synthesis |
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Timing closure tool |
Simulation
| EDA Vendor | Product Name | Design Solution |
|---|---|---|
| Aldec, Inc. | Active-HDL | Simulation |
| Riviera-PRO | Simulation | |
| Cadence Design Systems, Inc. | Xcelium Logic Simulator | Simulation |
| Mentor Graphics | ModelSim® | Simulation |
| Questa Advanced Simulator | Simulation | |
| Metrics Design Automation | Metrics Cloud Simulator (SaaS Cloud Computing Environment for simulation) | Simulation |
| SynaptiCAD | VeriLogger Extreme | Simulation |
| Synopsys | VCS | Simulation |
Verification
EDA Vendor |
Product Name |
Design Solution |
|---|---|---|
Design Rule Checking and Clock Domain Crossing (CDC) Verification |
||
| Blue Pearl | RTL checker |
|
Constraints generator |
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Clock Domain Crossing (CDC) |
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Formal verification |
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Constraints generator |
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Timing-exception verification |
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Timing-exception validation |
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Equivalence checking |
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Functional verification |
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Clock domain crossing verification |
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Clock domain crossing verification |
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Testbench generator |
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Timing verification |
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RTL analysis for FPGA designs |
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Lint checks |
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Clock domain crossing (CDC) verification |
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Functional property verification |
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Logic equivalence checking |
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In-system verification and integrated RTL debug |
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In-system verification |
Board-Level Design
EDA Vendor |
Product Name |
Design Solution |
|---|---|---|
PCB board schematics and layout |
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FPGA I/O planning |
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SI analysis |
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Allegro Design Authoring |
PCB board schematics |
|
PCB board schematics |
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PCB board layout |
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PCB board layout |
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| Keysight Technologies | PathWave Design Software | PathWave Advanced Design System (ADS) |
FPGA I/O planning |
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SI analysis |
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PCB board schematics |
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PCB board schematics and layout |
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PCB board layout |
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PCB board layout |
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Signal Integrity Software, Inc. (SiSoft) |
SI analysis |
ASIC Prototyping
Design Optimization
All EDA Partners
ACCESS Program Partner |
System- Level Design |
Design Creation |
Synthesis |
Simulation |
Verification |
Board-Level Design |
ASIC Prototyping |
Design Optimization |
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