India Mobile Congress 2026

Oct 7 – 10 | New Delhi, India | Hall 2, Meeting Room 2-MR-R11

Programmable Intelligence Across Every Network

Altera will be attending IMC New Delhi, October 7th to 10th, 2026 and look forward to meet with teams in network/wireline, wireless and satellite communications during the event to discuss our latest solutions, technologies, and demos to help you shape what’s next across every network.

Late-stage 5G, early 6G, and emerging non-terrestrial networks are transforming the wireless landscape, driving expansion across new spectrum, architectures, and environments. To keep pace, innovators need flexible, proven platforms that reduce risk, accelerate time-to-market, and adapt quickly as requirements evolve. As AI increasingly shapes network intelligence and optimization, learn how Altera bridges real-time networking and AI, enabling smarter and more adaptive systems for future-ready scalability.

If you are interested in meeting us at IMC schedule a meeting with events@altera.com.

India Mobile Congress Demo Overview

AI: Channel Estimation

This demo showcases AI-driven channel estimation using CNN and MLP neural networks deployed on Altera® SoC FPGAs. Traditional techniques like LS and MMSE struggle in noisy environments, but this AI-based approach delivers up to 20% higher throughput, lower EVM, and 67% reduction in DSP resources. The design flow combines MATLAB, DSP Builder, and FPGA AI Suite for rapid deployment to 5G radio units.

AI: Small Language Model

Altera® SoC FPGAs bring generative AI to the embedded edge with on-device Small Language Model inference. This demo shows how SLMs can run directly on Agilex™ FPGAs, delivering low-latency natural language processing without cloud connectivity. The FPGA AI Suite transforms high-level AI models into optimized RTL, enabling real-time conversational AI for industrial HMI, voice assistants, and IoT applications.

AI: DPD Toolflow

The Altera® DSP toolflow integrates AI models with classical DSP techniques using a unified environment powered by DSP Builder Software. This demo shows how developers can evaluate precision, resource usage, and performance in a single workflow to create optimized AI/DSP hybrid designs for applications like Digital Pre-Distortion. The flow supports rapid iteration from MATLAB model to FPGA deployment.

AI: CSI Compression

This demo achieves up to 1000x Channel State Information compression using an autoencoder neural network on Altera® Agilex™ SoC FPGAs while maintaining greater than 0.9999 correlation accuracy. By dramatically reducing uplink signaling overhead, this solution enables denser 5G deployments supporting more users per cell. Built with the FPGA AI Suite and OpenVINO™ toolkit, the design supports 3GPP Rel-17 standards.

AI: Timing Synchronization

This demo shows how MLP and LSTM neural networks deployed on Altera® SoC FPGAs can predict clock drift during GNSS holdover events, keeping RAN networks synchronized when GPS signals are unavailable. The AI-powered approach delivers up to 10x reduction in power consumption and cost compared to traditional high-stability oscillator solutions. The design uses the FPGA AI Suite alongside Altera's PTP Servo IP.

AI: Sensing (ISAC)

Altera® SoC FPGAs enable Integrated Sensing and Communication (ISAC)—a foundational 6G technology that transforms wireless infrastructure into dual-purpose systems for both communication and radar-like sensing. This demo uses Remote Radio Heads with neural network models to detect and track objects using the same radio signals and hardware used for communication. The AI-enhanced solution delivers low-latency environmental awareness for smart cities, industrial automation, and autonomous systems.