banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

Loading

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

12G SDI FMC Card - VIDIO

Nextera's VIDIO 12G SDI FMC Card has been chosen by Altera for use in their SDI reference designs, including Agilex®, Cyclone®, and Stratix® development kits. The VIDIO FMC card is made in the USA, utilizes the latest generation Texas Instruments chips for unrivaled quality and jitter performance, and does not require any software to initialize. Each purchase includes access to the user guide, reference designs, schematics, assembly drawings, BOM, and more.

Offerings Image

12G-SDI Broadcast 4K Video, Low Latency Stereo 3D Surgical Imaging

12G-SDI Broadcast 4K Video, Low Latency Stereo 3D Surgical Imaging

1G Deep Buffering Memory Ethernet Switch

make it even shorter12:18 PMClaude responded: Comcores' 1G Deep Buffering Ethernet Switch IP offers external RAM buffering, fine-grained traffic prioritization, and per-port/queue egress shaping, with supp…Comcores' 1G Deep Buffering Ethernet Switch IP offers external RAM buffering, fine-grained traffic prioritization, and per-port/queue egress shaping, with support for MAC learning, VLAN 802.1Q, multicast, and IEEE 1588 transparency

40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency.

40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

4G LTE/LTE-A CTC

Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

MLE 50G TCP/IP is a stand-alone TCP/IP Stack Full Accelerator Subsystem allowing 50Gbps communication at full line rate and low latency. It includes TCP, IP, MAC Layer, supports 128-bit wide full duplex data width, and pipelines all-RTL implementation for high throughput and ultra low Latency.

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low Latency.

Offerings Image

Achieving Timing Closure

The most comprehensive timing training which deals with simple and very complex, low and high speed timing violation. Write complex SDC files for advanced use cases. Analyze timing violation and apply a solution from an arsenal of options. Use the device architecture and tricks to solve complex issues.