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High-Level Synthesis (HLS) for FPGA Acceleration
This course provides comprehensive training in the Altera HLS Compiler Pro Edition.
By FPGA Authority
High-performance Debugger and Parallel Trace for Nios II (E/F/S)
PowerDebug X51 (USB3 and Ethernet) with PowerTrace III 8 GB includes Preprocessor for Nios® II, PowerView software, debug license and 1 year maintenance.
By Lauterbach GmbH
HLS, OpenCL, and RTL for AI Inference and Acceleration
This advanced course develops the skills to design, optimize, and integrate custom AI inference accelerator kernels using Altera HLS Compiler Pro, the Altera FPGA SDK for OpenCL, and RTL/SystemVerilog on Altera FPGAs.
By FPGA Authority
HMAC-SHA256 accelerator
Chevin Technology’s HMAC‑SHA256 cryptographic accelerator provides fast, secure generation and verification of message authentication codes, enabling trusted communication between senders and receivers. Implemented as an all‑RTL solution, it efficiently computes SHA‑256 hashes and HMAC codes for messages of any length, supporting multiple parallel data streams limited only by available memory. It is ideal for high‑security, high‑throughput applications—such as cybersecurity, defense, and aerospace—where CPU‑based solutions cannot meet performance and security requirements
By Chevin Technology Limited
HPS Peripherals, Drivers & Device Tree Development
Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices.
By FPGA Authority
HSDLC: HDLC & SDLC Protocol Controller Core
The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.
By Computer Aided Software Technologies, Inc (dba CAST)
HSMC Video Development, Low Latency Video Up-scaler & Chroma Keyer
HSMC Video Development, Low Latency Video Up-scaler & Chroma Keyer
By Orchid Technologies Engineering and Consulting, Inc.
HSR & PRP Network Redundancy (IEC62439-3)
Full standalone hardware only solution of a HSR & PRP Network Redundancy Dual Attached Node (DAN) and RedBox
By NetTimeLogic GmbH
HyperBus Controller (Silicon Proven IP for Altera Devices)
Mobiveil’s HyperBus Controller enables high-speed (up to 333 MB/s) flash access over a 12-pin interface, surpassing legacy SPI/QSPI protocols. It supports AXI interface, 0-wait-state writes, continuous burst reads, and XiP execution. Ideal for HyperFlash/HyperRAM integration, it maximizes throughput and performance in constrained systems.
By Mobiveil Inc.
