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Marx High Voltage Pulse Generator, Cardiac Ablation Surgery
Marx High Voltage Pulse Generator, Cardiac Ablation Surgery
By Orchid Technologies Engineering and Consulting, Inc.
Marx High Voltage Pulse Generator, Pulsed Energy Systems
Marx High Voltage Pulse Generator, Pulsed Energy Systems
By Orchid Technologies Engineering and Consulting, Inc.
Mastering Altera AI Suite
This course provides comprehensive, hands-on expertise with the Altera FPGA AI Suite.
By FPGA Authority
MIPI H.264
The MIPI H.264 IP Core is a high-performance, low-latency video encoder/decoder solution designed for real-time video compression and decompression based on the ITU-T H.264 / MPEG-4 AVC standard.
By Qbit Labs Incorporation
Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design
MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.
By Missing Link Electronics
ML/AI Essentials for Hardware Engineers
This foundational course provides hardware engineers, FPGA designers, and embedded software engineers with the machine learning and deep learning knowledge required to participate effectively in AI hardware acceleration projects.
By FPGA Authority
MPEG2 Video Decoder
Fabric only, MPEG2 Decoder IP core HD60 Decoding supporting interlaced and progressive.
By System-On-Chip Technologies Inc.
MPEG2 Video Encoder
Legacy MPEG2 Video Encoder IP core Supporting HD Progressive and Interlaced formats Runtime API
By System-On-Chip Technologies Inc.
MSC-CTRL Microsecond Channel high-speed controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect an SoC to external power devices or sensors. It implements the Microsecond Channel (MSC) protocol and acts as a bus master for downstream and as a bus slave for upstream transfers. The MSC-CTRL is integrated to peripherals via high-speed synchronous downstream and low-speed asynchronous upstream channels. It supports up to four slave devices in the MSC mode, advanced features, fragmented command frames, and higher upstream baud rates, provide robust communication in a network of dedicated sensors or devices. The IP includes a 32-bit AMBA® APB4 subordinate interface and includes trigger signals to facilitate easy integration with an external DMA controller. The silicon-proven MSC-CTRL core is designed to industry best practices and has been rigorously verified. Optional functional safety documents facilitate ISO 26262 ASIL B standard.
By Computer Aided Software Technologies, Inc (dba CAST)
