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O-RAN FPGA IP
Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.
By Altera
Octal SPI DDR PSRAM Controller
Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory size. Thus any wearable design requires low power, lower RAM density and simplified inter face with optimal performances. These design requirements make PSRAM a natural choice for wearable applications. PSRAM has the advantages that there is no need of refresh control from external sources (unlike SDRAM) and active and standby currents are very low, therefore it has been adopted in many battery-operated mobile applications such as cellular phones and recently making its way into wearables and loT applications.
By Mobiveil Inc.
Optical Coherence Tomography (OCT), High Speed Multi-Channel Data Acquisition System
Optical Coherence Tomography (OCT), High Speed Multi-Channel Data Acquisition System
By Orchid Technologies Engineering and Consulting, Inc.
Optical Transport
We offer both OTN applications, such as Add/Drop Multiplexer (ADM), Muxponders, Transponders, Regenerators etc, for speeds from 1Gbps to 1.6 Tbps. Client support of Ethernet, Fibre Channel, OTN, SONET, and SDH. Line support of FlexO and OTU.Including all overhead processing, synchronization, software API / SDK
By Zeuxion ApS
Optically Coupled Precision Timing
Optically Coupled Precision Timing
By Orchid Technologies Engineering and Consulting, Inc.
Packet Switching
We offer UltraEthernet and RoCEv2, GPON, XGS-PON,25G-PON & 50G-PON, Ethernet from 1G to 1.6T PCS/MAC/FEC, Packet Processing, Traffic Managers, 4G & 5G Mobile Front and Backhaul, Sub-nanosecond timestamping, MPLS-TP & Ethernet OAM, IP4&IP6 forwarding, 1588v2 and SYNC-E, Datacenter Offload, 600G FlexEthernet, vEPC, 100G PLE
By Zeuxion ApS
Partial Reconfiguration with Altera FPGAs
Partial Reconfiguration (PR) allows a defined region of an FPGA to be reconfigured at runtime while the remainder of the device continues to operate without interruption.
By FPGA Authority
PCB Design Services
PCB design, including supply chain under ODM model, includes complex high-speed systems, RF systems up to 120GHz, and mixed-signal PCBs.
By TES Electronic Solutions GmbH
PCIe to SRIO Bridge Controller (FPGA IP for Altera Devices)
This Gen3 PCIe to SRIO Bridge enables full-speed protocol conversion with advanced messaging and DMA engines. Supporting aerospace, telecom, defense, and HPC, it ensures low-power, compact implementation. Ideal for embedded systems, it bridges PCIe versatility with SRIO performance.
By Mobiveil Inc.