.webp){kind=small}
Loading
RunX Low-Latency H.264 Video Encoder IP Core
Low-latency, hardware-optimized H.264/AVC video encoder IP core suitable for both FPGA and ASIC implementations in real-time embedded systems.
By RunX Technology
Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
The UHT-JPEG-D core from Alma Technologies is an ultra-high throughput 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed to provide all the power needed in modern image and video compression applications.
By Alma Technologies S.A.
Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
The UHT-JPEG-E core from Alma Technologies is an ultra-high throughput 8-bit Baseline and 10/12-bit Extended hardware JPEG encoder with optional video rate control functionality.
By Alma Technologies S.A.
Scalable Ultra-High Throughput Image and Video Scaler
The UHT-SCALER core provides a video processing block which converts input video frames of one size and sampling format to output frames of a different size and/or sampling format.
By Alma Technologies S.A.
Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
UHT-DSC-D
By Alma Technologies S.A.
Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
UHT-DSC-E
By Alma Technologies S.A.
SCR: Smart Card Reader Controller
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.
By Computer Aided Software Technologies, Inc (dba CAST)
SDC Constraints and Analysis Masterclass
This course provides FPGA engineers with a comprehensive, hands-on mastery of Synopsys Design Constraints (SDC) authoring and static timing analysis (STA) using the Quartus® Prime Pro Edition Timing Analyzer.
By FPGA Authority
SDI II FPGA IP
The Altera SDI II FPGA IP core enables high-performance serial digital interface (SDI) transmission and reception across SD, HD, and 3G to 12G video rates.
By Altera
