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Securyzr - Post-Quantum Cryptography
THE FIRST WORLDWIDE PQC READY SECURE SOLUTION FROM CHIP TO CLOUD
By Secure-IC SAS
Securyzr iNTEGRATED SECURITY SERVICES PLATFORM
A CHIP TO-CLOUD COMPLETE SECURITY SOLUTION
By Secure-IC SAS
Securyzr™ iSE Root of Trust solutions
Securyzr™ iSE is Secure-IC Root of Trust solution. Embedded in an FPGA or SOC designs, it offers multiple services to its host system: secure boot, key isolation, anti-tampering protection, etc. Thanks to its dual computation and strong isolation, it offers an additional layer of security compared to trusted execution environments.
By Secure-IC SAS
Securyzr™ Xperience
Securyzr™ Xperience offers a complete, ready-to-use platform to explore, integrate, and validate cutting-edge security features.
By Secure-IC SAS
Semiconductor Wafer Fabrication Equipment, Supply Chain Rapid Electronic Product Redesign
Supply Chain Rapid Electronic Product Redesign
By Orchid Technologies Engineering and Consulting, Inc.
Sensor Fusion & Autonomous Systems
Multi-modal sensor fusion design services on Agilex and Stratix — LiDAR, radar, EO/IR, IMU, and GNSS integration for autonomous and C5ISR platforms.
By Integral & Open Systems,Inc
SHA-256: 256-bit SHA Secure Hash Crypto Engine
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (2^64 – 1) bits. Developed for easy reuse in ASIC and FPGA applications, the SHA-256 is available optimized for several technologies with competitive utilization and performance characteristics. Support for AMBA bus interfaces and integration with an external DMA are available as options "
By Computer Aided Software Technologies, Inc (dba CAST)
SHA-3: Secure Hash Crypto Engine
The SHA-3 IP core is a high-throughput, area-efficient hardware accelerator for SHA-3 cryptographic hashing, compliant with NIST FIPS 180-4 and FIPS 202. It operates independently of a host processor, using AMBA® AXI4-Stream interfaces for input and output. An optional AXI4-Stream to AXI4 Memory Mapped bridge, with or without DMA, can be used. A single core instance implements all fixed-length and extendable-output hash functions, with function and output length (up to 2 GB) selectable at runtime per input message. The core is highly configurable at synthesis, including bus width and SHA-3 permutation rounds per cycle, enabling throughput–area trade-offs. One permutation per cycle processes 50 bits per cycle, scaling to over 100 Gbps with multiple permutations in modern ASICs. Fully synchronous, single-clock, scan-ready, LINT-clean, it uses only rising-edge flip-flops, with no false or multi-cycle paths, simplifying integration and verification.
By Computer Aided Software Technologies, Inc (dba CAST)