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TOD Slave ( Time of Day, NMEA, UBX, TSIP, ESIP)
Full standalone hardware only solution of a TOD Slave
By NetTimeLogic GmbH
Training Partner
Gaining knowledge and skills is crucial in the world of electronics development to stay competitive in today’s fast growing world of technology. Do you wish to enhance your design skills so you can complete your projects faster? Sign up for one of our training in the field of electronics development tooling and design methodology.Altera FPGA training: - Introduction to VHDL. - Advanced VHDL Design Techniques. -Quartus® Prime Design Software: Foundation. - Introduction to the Platform Designer System Integration Tool (Qsys). - Designing with Nios® II Processor. -Quartus® Prime Software: Timing Analysis with Timing Analyzer. - Designing with an ARM-based SoC.Go to the website of Transfer DSW B.V and make a selection from the list of available trainings dates.
By Transfer DSW B.V.
TSN End-Node (IEEE802.1 Time Sensitive Networking End-Node)
Full standalone hardware only solution of a TSN End-Node
By NetTimeLogic GmbH
TSN Network Node (IEEE802.1 Time Sensitive Networking Switched End-Node)
Full hardware only solution for a TSN Switched End-Node
By NetTimeLogic GmbH
TSN-EP-10G: 10G TSN Ethernet Endpoint Controller
The TSN-EP-10G is a highly configurable TSN Ethernet Endpoint Controller IP core designed to streamline the implementation of Time-Sensitive Networking endpoints. It provides hardware support for 802.1AS-2020, 802.1Qav, 802.1Qbv, optional 802.1Qci and 802.1Qcc. It includes a low-latency Ethernet MAC with XGMII PHY interface and AXI-Stream Host interface. The core delivers precise, deterministic latencies with minimal host software required and provides real-time timing information along with dynamic traffic-shaping adjustments. Designed for simple integration, TSN-EP-10G uses standard AMBA® interfaces: a 32-bit APB for CSR and a 128-bit AXI-Streaming interface for data packets. Optional DMA is also available. Delivered as synthesizable RTL or FPGA netlist, it includes testbenches, sample scripts, documentation and a lightweight gPTP for FreeRTOS and Linux. Suitable for automotive, industrial, aerospace, and other applications requiring low-latency, deterministic TSN communication.
By Computer Aided Software Technologies, Inc (dba CAST)
TSN-EP: TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).
By Computer Aided Software Technologies, Inc (dba CAST)
TSN-SE: TSN Ethernet Switched Endpoint Controller
"The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available.
By Computer Aided Software Technologies, Inc (dba CAST)
TSN-SW: TSN Ethernet Switch
The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.
By Computer Aided Software Technologies, Inc (dba CAST)
Turbo-V FPGA IP Core
Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.
By Altera
