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UDP/IP Offload Engine
Chevin Technology’s UDP Ethernet IP core delivers low‑latency, high‑throughput connectivity across 10G–200G networks, with efficient packet handling and minimal overhead. It simplifies integration with an AXI4‑Streaming interface, supports multi‑port configurations, and provides a proven, scalable solution for high‑performance networking applications.
By Chevin Technology Limited
UDPIP-100G: 100G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UDPIP-10G/25G: 10G/25G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 25 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UDPIP-1G: UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 10 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UHS OPI PSRAM Controller (Silicon Proven IP for Altera Devices)
Targeted at wearables and low-power devices, Mobiveil’s UHS OPI PSRAM Controller supports AP Memory’s UHS series running up to 1066 MHz. It delivers low-power, high-frequency performance for memory subsystems with simplified interface requirements. The flexible architecture ensures precise control signal timing for seamless SoC integration.
By Mobiveil Inc.
Ultra-high-throughput WiFi LDPC Decoder
XCEL ASICs’ Ultra-High-Throughput Wi-Fi LDPC Decoder IP is an IEEE 802.11n/ac/ax/be–compliant (Wi-Fi 4/5/6/7) forward error correction (FEC) solution optimized for current and next-generation Wi-Fi transceivers and SoC designs. In addition to supporting earlier Wi-Fi generations, the IP enables Wi-Fi 7 (IEEE 802.11be) data rates exceeding 30 Gbps while delivering exceptional throughput-per-area efficiency, enabling very high decoding performance within a minimal silicon footprint. This combination of scalable throughput and area efficiency makes the IP particularly well suited for cost- and power-constrained, high-performance Wi-Fi transceiver chip implementations.
By XCEL ASICs LLC
Ultrahigh Definition 4K Video Processing, Altera Agilex® FPGA Solution Using VIP
Ultrahigh Definition 4K Video Processing, Altera Agilex® FPGA Solution Using VIP
By Orchid Technologies Engineering and Consulting, Inc.
Understanding Device Architecture
This course is offered as core material followed by two independent optional sessions. The core material provides the essential, device family agnostic foundation every engineer needs before working with any Altera FPGA or SoC FPGA.
By FPGA Authority
