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Altera® FPGA Design Services / IP Design Services - MLE
MLE offers FPGA design services for Altera® FPGAs, which give a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built-in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power, and cost.
By Missing Link Electronics
Applied Formal Verification
This is the foundation course of a two course formal verification progression. It delivers a complete, hands-on grounding in formal methods using SystemVerilog Assertions and the Questa Formal tool flow
By FPGA Authority
Arm TrustZone Technology
Arm TrustZone technology provides a cost-effective methodology to isolate security critical components in a system, by hardware separating a rich operating system, from a much smaller, secure operating system. This training covers all aspects of TrustZone from CPU level up to system level, including debug, exception handling, virtualization, MMU, secure boot, and system architecture.
By HandsOn-Training
ASCON-F: ASCON Authenticated Encryption & Hashing Engine
The ASCON-F IP is a compact, high-throughput HW core implementing the lightweight authenticated encryption with associated data (AEAD) & hashing algorithms of the Ascon v1.2 spec. A single instance supports encryption & decryption with Ascon-128 & Ascon-128a, as well as cryptographic hashing with Ascon-Hash & Ascon-Hasha. Operation mode, key, and nonce values are run-time programmable & can change per input block. The core provides simple I/O I/F, optionally bridged to AXI4-Stream or AXI4 Memory Mapped ports through CAST bridges. It synthesizes to ~11k gates & runs at over 2GHz in modern ASIC technologies. Excluding padding & initialization, throughput ranges from 5.3 to 16 bits/cycle, or 10.6 to 32Gbps at 2GHz, with higher throughput possible by instantiating multiple cores. Easy to use & integrate, following best coding & verification practices, has no multi-cycle or false paths, uses only rising-edge D flip-flops, no tri-states or SRAMs, and operates in a single clock/reset domain.
By Computer Aided Software Technologies, Inc (dba CAST)
Ashling's RiscFree for Altera FPGAs
Altera has partnered with Ashling to make Ashling’s RiscFree™ SDK available for Altera FPGAs. The partnership includes full Unified Debugger support for the FPGA Arm hard cores and the Nios V soft processors.
By Ashling Microsystems Ltd.
ASRC: Audio Sample Rate Converter
The CAST ASRC (Audio Sample Rate Converter) is a compact, high-performance IP core that delivers precise digital audio conversion across a wide range of sample rates (8 kHz to 192kHz) while preserving signal integrity and minimizing distortion. Supporting both asynchronous and synchronous modes, it ensures seamless real-time streaming or high-speed batch processing for applications in professional audio, broadcast, telecommunications, automotive infotainment, gaming, and VR. The ASRC handles tens to hundreds of TDM channels, achieving ultra-low distortion with THD+N averaging -130 dB. With sub-100ms sync time and minimal latency, it provides transparent, studio-grade 24-bit audio conversion. Designed for easy integration into ASICs or FPGAs, it features AXI4-Stream for audio data, AXI-Lite/APB control interfaces, and optimized resource usage for cost-sensitive environments. Deliverables include Verilog RTL/netlist, testbenches, drivers, and documentation for rapid deployment
By Computer Aided Software Technologies, Inc (dba CAST)
ATSC 8-VSB Modulator
The CMS0033 ATSC 8-VSB modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
By Commsonic Ltd
Aurora 64B/66B IP Core
The ALSE Aurora 64B/66B is a complete and fully compliant implementation of the published protocol. It allows to interconnect Altera FPGAs to Altera and other vendors FPGAs through High-Speed Serial links, from 1Gb/s to 800 Gb/s.
By ALSE Advanced Logic Synthesis for Electronics
Aurora 8B/10B IP Core
The ALSE Aurora 8B/10B IP Core makes this open protocol available to all Altera FPGAs (that include transceivers).
By ALSE Advanced Logic Synthesis for Electronics