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AV153 VPX Board

SOSA-aligned VPX board, designed for electronic warfare and signal processing applications. Unlike many competing solutions, it offers an optimal combination of high-performance FPGA, ultra-low latency and native compatibility with open architectures.

Baseline JPEG Video Decoder IP Core

This compact, extremely efficient and low latency IP core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs. This IP does not require any processor nor any external memory.

Baseline JPEG Video Encoder IP Core

Very compact and very low latency JPEG/MPEG encoder ideal for video and still pictures. Output is fully standard and decoded by all viewers.

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Board Design Services

High Speed Board Design

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BoardTrace

Visualize and verify connectivity between PCBs and large components (including configurable microcontrollers and FPGAs) on connected PCBs. Independent of netlist formats and connection styles (backplanes, connectors, and/or rear panels). Includes connector mapping for VPX connectors.

BxBChan Channelizer

An efficient implementation of a Polyphase Filter Bank channelizer.

BxBFFT Fast Fourier Transform

An extraordinarily Fast, Efficient, and Feature-Packed FFT implementation.

CAN-CTRL: CAN 2.0, CAN FD, & CAN XL Bus Controller Core

"The CAN-CTRL is a CAN bus controller compliant to Classical CAN, CAN FD, and CAN XL. The core is easy to use and integrate, featuring programmable interrupts, data and baud rates; and a configurable number of independently programmable acceptance filters. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). Finally, the CAN-CTRL provides error analysis, diagnosis, maintenance, and optimization features. The CAN-CTRL is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready. "

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Catalyzr™ Security Risk Assessment (SW)

Catalyzr leverage a tool-based approach to guide the correct usage of crypto-APIs, then developers can benefit from the expertise and experience of cryptographic specialists, ensuring more robust and secure implementations of cryptographic functionality within their applications