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Cortex-A76 Software Development
Agilex® 5 implements Armv8.2 architecture which has many benefits. This training covers all new architecture features, guide engineers how to utilize the new features and optimize performance, code density, power consumption, and debug. Extensive hands-on labs to practice all necessary aspects of the CPU.
By HandsOn-Training
CPU-less NVMe Host Controller IP core for PCIe Gen3 (NVMe IP)
NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the integrated PCIe® Gen3 block on Altera FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost.
By DesignGateway Co., Ltd.
CPU-less NVMe Host Controller IP core for PCIe Gen4 (NVMe IP)
NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the P-tile on Agilex® 7 FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost
By DesignGateway Co., Ltd.
CPU-less NVMe Host Controller IP core for PCIe Gen5 (NVMe IP)
NVMe-IP core is a standalone NVMe™ Host Controller designed for seamless integration with the R-tile on Agilex® 7 FPGA devices. It eliminates the need for a CPU or external memory, simplifying system complexity while delivering high-performance NVMe SSD interfacing—ideal for applications requiring speed, simplicity, and efficiency. Included reference designs for Altera FPGA boards help accelerate NVMe storage development, reducing both time and cost.
By DesignGateway Co., Ltd.
Creonic 5G NR LDPC Decoder and Encoder
Creonic’s 5G LDPC Decoder and Encoder IP cores provide a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.
By Creonic GmbH
Creonic CCSDS 131.2 Wideband Demodulator
The Creonic CCSDS high performance wideband demodulator performs all tasks of an inner receiver.
By Creonic GmbH
Creonic CCSDS 131.2 Wideband Modulator
The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter.
By Creonic GmbH
Creonic CCSDS AR4JA LDPC Encoder and Decoder
The Creonic CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
By Creonic GmbH
Creonic DOCSIS 3.1 LDPC Decoder IP cores (PLC / NCP / Data)
The Creonic DOCSIS 3.1 LDPC decoder IP cores are a complete solution for the downstream forward error correction, i.e. PLC decoder, NCP decoder and data decoder are included.
By Creonic GmbH