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Achieving Timing Closure
The most comprehensive timing training which deals with simple and very complex, low and high speed timing violation. Write complex SDC files for advanced use cases. Analyze timing violation and apply a solution from an arsenal of options. Use the device architecture and tricks to solve complex issues.
By HandsOn-Training
Achilles Arria® 10 SoC SoM
This module is based on an altera® Arria® 10 SoC FPGA, combining FPGA performance with embedded ARM processing for flexible and compact system designs. It integrates DDR4 memory with ECC and supports multiple high-speed interfaces, enabling the development of scalable, high-performance embedded applications.
By reflex ces
Adjustable Clock
Full standalone hardware only solution of an adjustable Counter Clock
By NetTimeLogic GmbH
Advanced Formal Verification
This is the advanced course of a two course formal verification progression. It assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that dominate real Altera SoC designs.
By FPGA Authority
Advanced FPGA Design Methodologies and Techniques
This comprehensive course consolidates the full breadth of advanced FPGA design knowledge into a single intensive program.
By FPGA Authority
Advanced Platform Designer
This advanced course elevates engineers from solid Platform Designer users to expert-level practitioners.
By FPGA Authority
Advanced SoC System Design & Verification
This advanced course brings together all disciplines of Altera SoC FPGA design into a comprehensive system design and verification experience.
By FPGA Authority
Advanced Verilog Design Techniques
This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices.
By FPGA Authority
Advanced VHDL
This advanced, hands-on course is designed for experienced FPGA engineers who want to deepen their mastery of VHDL.
By FPGA Authority