banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
Partner Solutions Partner Solutions
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

HawkEye-CL: Camera Link Frame Grabber & Image Processing

The HawkEye-CL Frame Grabber is Camera Link Rev. 2.0 compliant, offering a number of options, from plug-and-play grabbers to a full system solution that includes acquisition and on-FPGA processing. The card is supported by off-the-shelf modular building blocks for embedding in the acquisition pipeline, including HDR, white balance, gamma correction, compression (JPG, lossless, Quality+), and more. It is also supported by Gidel's InfiniVision acquisition architecture, optimized for grabbing from 100+ cameras.

HawkEye-CXP12: CoaXPress-12 Frame Grabber & Image Processing

The HawkEye-CXP12 is a 4 x CoaXPress-12 Frame Grabber card with option for real-time image processing and compression. The card is supported by off-the-shelf modular building blocks for embedding in the acquisition pipeline, including HDR, white balance, gamma correction, compression (JPG, lossless, Quality+), and more. It is also supported by Gidel's InfiniVision acquisition architecture, optimized for grabbing from 100 + cameras

HDMI Reciver Transmitter Cores

The HDMI Transmitter core is has a very low footprint and works at various speed depending on application being used.

HDMI-FMC Daughter Card

Terasic HDMI-FMC is a HDMI transmitter/receiver daughter board with FMC (FPGA Mezzanine card) interface. The user can connect the HDMI module with the FPGA development kit via the FMC connector for HDMI image & video capturing, processing and displaying up to 4Kx2K@30fps resolution.

HDR MODEM

A High Data Rate (HDR) modem enables reliable transmission of large volumes of data over communication channels with high efficiency. In the transmitter, the input data packet is first protected using CRC, then divided into smaller blocks and encoded using powerful forward error correction such as Low-Density Parity-Check Code. The encoded data undergoes rate matching and interleaving to improve robustness against channel errors before transmission. At the receiver, the process is reversed: the received soft information is deinterleaved, rate-adapted, and decoded using LDPC decoding. Finally, a CRC check verifies the correctness of the recovered data, ensuring reliable high-speed communication.

Heronic AI Accelerator Design Services

Heronic Technologies offers specialized design services for bespoke AI accelerator architectures on FPGAs, utilizing in-house automation and an IP portfolio to meet the unique demands of diverse AI applications like object detection and image classification. This approach directly tackles the inefficiency of generalized hardware in Edge AI and TinyML, enabling the rapid development of highly efficient, streaming-based accelerators. As a result, Heronic delivers unparalleled performance and microsecond latency, evidenced by state-of-the-art results on MLPerf Tiny and superior outcomes compared to GPU offerings.

Offerings Image

High Definition Low Latency Stereo Camera, Robotic-Assist Surgical Video Electronics

High Definition Low Latency Stereo Camera, Robotic-Assist Surgical Video Electronics

Offerings Image

High Definition Stereo Image Processor, Medical Electronics

High Definition Stereo Image Processor, Medical Electronics

Offerings Image

High Definition Stereo Video Imaging, HD-SDI Medical Imaging Design

High Definition Stereo Video Imaging