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AES-CCM: Authenticated Encrypt/Decrypt Engine
The AES-CCM IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-CCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-CCM-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. CCM stands for Counter with CBC-MAC mode. CCM is a generic authenticate-and-encrypt block cipher mode. CBC-MAC is utilized to generate an authentication string while CTR mode is used to encrypt. The AES-CCM core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
By Computer Aided Software Technologies, Inc (dba CAST)
AES-GCM: Authenticated Encrypt/Decrypt Engine
The AES-GCM IP core implements NIST Advanced Encryption Standard (AES) in Galois Counter Mode (GCM). GCM is an authenticate-and-encrypt block cipher mode where a Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt. The core processes 128-bit blocks and is programmable for 128-, 192-, and 256-bit keys. Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S), more compact using a 32-bit datapath, requires 44/52/60 clocks for each data block (128/192/256-bit key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requires 11/13/15 clocks for each data block depending on key size. For high-throughput applications there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.
By Computer Aided Software Technologies, Inc (dba CAST)
AES-P: Programmable Advanced Encryption Standard Engine
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. The core works with a pre-expanded key, or with optional key expansion logic. The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
By Computer Aided Software Technologies, Inc (dba CAST)
AES-XTS: Storage Encrypt/Decrypt Engine
The AES-XTS encryption IP core implements hardware encryption/decryption for sector-based storage data. It uses the AES block cipher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths. Two architectural versions are available to suit system size and throughput requirements. The High Throughput XTS-X is more compact and can process 128 bits/cycle independent of the key size. The Higher Throughput XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path. XTS (XEX-based Tweaked Codebook Mode with Ciphertext Stealing) is a mode of AES that has been specifically designed to encrypt fixed-size data where a possible threat has access to the stored data.
By Computer Aided Software Technologies, Inc (dba CAST)
Agilex 7 I-Series 041b 3UVPX Plug In Module
A 3U VPX card featuring an Agilex 7 I-Series FPGA with 4 F-tiles, designed to deliver high-performance connectivity via PCIe Gen 4 and 40G Ethernet. Optimized for defense, aerospace, and high-performance computing systems. Supports high-bandwidth applications, real-time data processing, and secure communications.
By ForwardEdge ASIC, LLC
Agilex 9 R17B Direct RF Wideband PCIe Card: iG-G67P
The Agilex® 9 R17B Direct RF Wideband PCIe® Card is a high-performance RF platform based on the Agilex® 9 AGRW014 SoC FPGA, integrating 4 ADC and 4 DAC channels up to 64 GSPS, PCIe® Gen4 x8 connectivity, FMC+ expansion, and 58 Gbps PAM4 transceivers for advanced radar, wireless, aerospace, and test & measurement applications.
By iWave Global
Agilex Architecture Deep Dive
This course provides a comprehensive, ground-up treatment of the Altera Agilex FPGA and SoC device families.
By FPGA Authority
Agilex® 3 Development Kit: iG-G71D
The iG-G71D is a compact and feature-rich development kit built to evaluate Altera® Agilex® 3 SoC FPGA solutions. It offers comprehensive connectivity with 2.5G and Gigabit Ethernet, USB 3.0/2.0 via Type-C, PCIe Gen3 x4, and high-speed expansion through FMC+ and PMOD connectors. With additional interfaces including JTAG and a 20-pin HPS header (I2C, SPI, GPIOs), the G71D kit is ideal for prototyping embedded systems, industrial networking, and low-power edge applications.
By iWave Global
Agilex® 3 SoC FPGA SoM: iG-G71M
The iAgilex® 3 is a compact and power-efficient System on Module built on the Agilex® 3 C-Series FPGA with M16A package, designed for cost-sensitive, low-power edge applications. Featuring 4GB LPDDR4 (expandable to 8GB), 32GB eMMC storage, and 4 transceivers up to 12.5Gbps, it delivers up to 135K logic elements in a 50mm x 60mm form factor. With integrated PCIe Gen3 support and flexible memory and flash options, the G71M is ideal for industrial control, vision processing, and embedded computing at the edge.
By iWave Global