.webp){kind=small}
SystemVerilog for Verification
This course introduces engineers to developing comprehensive verification environments using SystemVerilog.
By FPGA Authority
tCAM IP
tCAM-IP is a high-performance, ultra-low-latency, and configurable Ternary Content-Addressable Memory IP, delivering deterministic search at 300 MSPS with a fixed latency of 7 clock cycles. It enables packet matching and filtering at up to 300 million packets per second over 40G/100G Ethernet. Ideal for applications such as packet filtering, intelligent switches/routers, deep packet inspection, and network security.
By DesignGateway Co., Ltd.
TCC IP
Turbo Convolutional Codes (TCC) are an advanced class of Forward Error Correction (FEC) techniques that provide near-Shannon limit performance in digital communications. Widely adopted in 3G, 4G LTE, satellite, aerospace, and defense-grade communication systems, TCCs significantly enhance data integrity and transmission reliability in noisy environments.
By Qbit Labs Incorporation
TCP/IP Offload Engine
Chevin Technology’s TCP/IP Offload Engine is a high‑performance, all‑RTL Ethernet stack that enables reliable, low‑latency network communication by offloading TCP/IP processing entirely into FPGA logic. It reduces CPU load, increases throughput, and simplifies integration, providing a scalable and efficient solution for network‑enabled applications
By Chevin Technology Limited
TCPIP-100G: 100G TCP/UDP/IP Hardware Stack
The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes.
By Computer Aided Software Technologies, Inc (dba CAST)
TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack
The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it autonomously opens, maintains, and closes TCP connections. Network parameters are configured via control registers, while data is exchanged over streaming interfaces. The core is highly configurable: up to 32,768 simultaneous TCP sessions can be supported, or just one for minimal area designs. Options include a DHCP client, reassembly of out-of-order packets, and integration of a UDP hardware stack with IGMPv3 multicast. Users may select cut-through mode for ultra-low latency and minimal buffering, or store-and-forward mode for verified, in-order delivery. Available in RTL or FPGA netlist form, the core is rigorously verified and provided with testbench, synthesis/simulation scripts, and full documentation, making it ideal for applications ranging from servers to edge devices.
By Computer Aided Software Technologies, Inc (dba CAST)
TEI0009 Cyclone® 10 LP FPGA Reference Kit
TEI0009 is a Cyclone® 10 LP FPGA reference kit for industrial development and general test applications. Revision 03 combines a 55 kLE FPGA with SDRAM, HyperRAM, flash memory, dual Fast Ethernet, analog I/O and an integrated USB programmer.
By Trenz Electronic GmbH
TEI0135 Agilex®3 SoC Module
TEI0135 is an Agilex®3 SoC module in development for industrial and test applications. The planned 40 × 56.4 mm design combines FPGA fabric and HPS with LPDDR4 memory, QSPI flash, eMMC storage, two Gigabit Ethernet PHYs, a MIPI CSI-2 receive interface and TPM 2.0.
By Trenz Electronic GmbH
TEI0140 Agilex® 3 Makerboard
TEI0140 is an Agilex® 3 FPGA makerboard in development for consumer applications and prototyping. The planned 35 × 73 mm board features up to 4 GB LPDDR4, QSPI flash, two 50-pin headers, a CRUVI-HS connector and an embedded USB Blaster III for JTAG and UART.
By Trenz Electronic GmbH