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XIP8001B True Random Number Generator (TRNG) IP Core
The True Random Number Generator (TRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essential for secure communications and cryptographic operations, such as key generation.
By Xiphera Ltd.
XIP8103B Pseudo Random Number Generator (PRNG) IP Core, balanced version
Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.
By Xiphera Ltd.
XIP8103H Pseudo Random Number Generator (PRNG) IP Core, high-speed version
Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.
By Xiphera Ltd.
XJAnalyser Module
XJTAG’s XJAnalyser module is a powerful tool for real-time circuit visualisation and debugging.
By XJTAG
XJDeveloper & XJDeveloper Plus - IDE for PCB test development
XJDeveloper is an Integrated Development Environment for development and execution of circuit tests.
By XJTAG
XJFlash Module
XJFlash is an advanced FPGA-based module that uses JTAG for accelerated in-system programming (ISP) of flash memories.
By XJTAG
XJRunner
XJRunner is a production test tool for high or low volumes with power diagnostics built in.
By XJTAG
XpressSX AGI-FH401G PCIe Gen5 Network Processing Board
The XpressSX AGI-FH401G is a PCIe Gen5 FPGA board based on an Intel® Agilex® 7 I-Series SoC FPGA, designed for ultra-high-speed networking and accelerated computing applications. Featuring up to 400GbE connectivity, high-bandwidth DDR4 memory, and low-latency architecture, it is optimized for SmartNIC, cybersecurity, and real-time packet processing workloads.
By reflex ces
xSPI-MC: xSPI, HyperBus™, and Xccela™ Serial Memory Controller
The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection, direct boot, and operation in multiple modes: Slave (AHB slave access), DMA (with internal DMA engine), Access In-Place (AIP) via AHB/AXI, and Boot-Image copy after reset. Compatible with single to 16x SPI devices, it offers flexible configuration through registers or an auto-configuration feature using a device list. Highly customizable via Verilog defines, it allows selection of DMA, auto-configuration, and device count. Delivered with a synthesizable soft-PHY, it is FPGA/ASIC ready and requires no process-specific dependencies.
By Computer Aided Software Technologies, Inc (dba CAST)
