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CoaXPress-over-Fiber Bridge Device IP core
Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.
By Sensor to Image GmbH
CoaXPress-over-Fiber Bridge Host IP core
Bridge IP Core for CoaXPress protocol to use Ethernet physical layer for data transfer.
By Sensor to Image GmbH
Comet A13 SOM
The Comet A13 SOM is Terasic's compact, production-ready System-on-Module powered by the Altera Agilex® 5 E-Series SoC FPGA. Combining FPGA fabric with Arm Cortex-A76 and Cortex-A55 processor cores, LPDDR4 memory, high-speed transceivers, and rich expansion I/O, it delivers a ready-to-deploy compute platform for edge AI, machine vision, robotics, and industrial automation
By Terasic Inc.
Comet A65 SOM
The Comet A65 SOM is Terasic’s production-ready System-on-Module built on Altera’s largest Agilex® 5 SoC FPGA (656K LEs). With integrated HPS/ARM, 12GB LPDDR4, and high-speed expansion connectors, it delivers a powerful, scalable platform for industrial edge applications — from robotics to medical imaging — all with a free Altera® Quartus® Pro Edition license included.
By Terasic Inc.
Compact Ethernet TSN Switch 10M/100M/1G/2.5G
Comcores' compact 10M–2.5G TSN Switch IP targets automotive, avionics, and industrial use, offering IEEE TSN compliance, cut-through switching, and the lowest market gate count, with MAC learning, VLAN 802.1Q, multicast, and 802.1AS timing support.
By Comcores ApS
Compute Express Link (CXL) IP
CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.
By Altera
Consulting for electrical characteristics of printed circuit boards
For signal transmission and noise problems in the development of electronic devices, especially those using Altera FPGA-based boards, we utilize our proprietary electronic measuring instruments and simulation software to identify issues and propose effective improvements.
By RITA Electronics, Ltd.
Cortex-A53 Software Development
Agilex® 7 and Agilex® 9 SoC implements Armv8.0 architecture which has many benefits. The training covers all new architecture features, guide engineers how to utilize the new features and optimize performance, code density, power consumption, and debug. Extensive hands-on labs to practice all necessary aspects of the CPU.
By HandsOn-Training
Cortex-A55 Software Development
Agilex® 5 HPS gets significant uplift, versus the prior architectures with dual Cortex-A76 plus dual Cortex-A55 plus DynamIQ Shared Unit (DSU) that forms the upgraded MPU architecture.Upgraded Application Processor Subsystem (APS). New Cache Coherency Unit (CCU), Generic Interrupt Controller (GIC), System Memory Management Unit (SMMU), and On-Chip RAM (OCRAM) that supports the new architecture
By HandsOn-Training