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GigE Vision 2.x Host IP Core
IP Core for GigE Vision 2.x compliant host/receiver applications.
By Sensor to Image GmbH
GigE Vision 3.0 Device IP with RoCEv2 Streaming
IP Core for GigE Vision 3.0 camera applications with support of remote DMA streaming using RoCEv2 protocol up to 25Gbps network speed.
By Sensor to Image GmbH
GROVF Full RDMA 100 Gbps
GROVF Full RDMA 100G enables high-performance RoCE v2 connectivity for FPGA-based SmartNIC, DPU, HPC, and scale-out networking systems. The solution combines FPGA programmability with standards-based RDMA performance for customers building customized, low-latency Ethernet fabrics.
By Grovf Inc.
GROVF Full RDMA 200 Gbps
GROVF Full RDMA 200G enables high-speed RoCE v2 connectivity for FPGA-based SmartNIC, DPU, HPC, and scale-out networking systems. The solution is designed for customers requiring higher bandwidth RDMA performance while maintaining FPGA-level customization and standards-based Ethernet integration.
By Grovf Inc.
GROVF Streaming RDMA 100 Gbps
GROVF Streaming RDMA 100G enables FPGA-based systems to stream sensor, camera, RF, or FPGA-generated data directly to remote CPU or GPU memory over RoCE v2 Ethernet. The solution is optimized for high-bandwidth, low-latency streaming without unnecessary CPU involvement or memory copies.
By Grovf Inc.
GROVF Streaming RDMA 200 Gbps
GROVF Streaming RDMA 200G enables high-speed FPGA-based streaming of sensor, camera, RF, or FPGA-generated data directly to remote CPU or GPU memory over RoCE v2 Ethernet. The solution is built for demanding streaming applications requiring higher bandwidth, low latency, and minimal CPU involvement.
By Grovf Inc.
GTS Ethernet Hard IP
The GTS Ethernet Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet compatible with the IEEE 802.3-2018 Standard and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.
By Altera
GTS PCIe Hard IP
GTS PCIe Hard IP is a full featured protocol stack with AXI4-Stream user interface available on Agilex® 5 and Agilex® 3 FPGAs.
By Altera
GUPF Peer Negotiation and Lane Discovery IP
Let peer endpoints establish a usable configuration despite lane ordering differences. A two-wire sideband negotiates profile, rate, protocol, link settings and active lanes.
By Garmo Labs
