.webp){kind=small}
Loading
Adjustable Clock
Full standalone hardware only solution of an adjustable Counter Clock
By NetTimeLogic GmbH
Advanced Formal Verification
This is the advanced course of a two course formal verification progression. It assumes comprehensive knowledge of “Applied Formal Verification” and applies formal methods to the problems that dominate real Altera SoC designs.
By FPGA Authority
Advanced FPGA Design Methodologies and Techniques
This comprehensive course consolidates the full breadth of advanced FPGA design knowledge into a single intensive program.
By FPGA Authority
Advanced Platform Designer
This advanced course elevates engineers from solid Platform Designer users to expert-level practitioners.
By FPGA Authority
Advanced SoC System Design & Verification
This advanced course brings together all disciplines of Altera SoC FPGA design into a comprehensive system design and verification experience.
By FPGA Authority
Advanced Verilog Design Techniques
This course teaches designers to write professional, synthesizable RTL code using industry-standard Verilog HDL practices.
By FPGA Authority
Advanced VHDL
This advanced, hands-on course is designed for experienced FPGA engineers who want to deepen their mastery of VHDL.
By FPGA Authority
AES - Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.
By Computer Aided Software Technologies, Inc (dba CAST)
AES 128 IP
AES-128 IP supports ECB mode for both encryption and decryption, processing 128-bit data blocks in a constant 11 clock cycles. It delivers 11.6 Mbps per MHz, achieving up to 4.65 Gbps at 400 MHz. Designed to enhance the security of data storage and networking IP cores, it enables secure, efficient, and high-performance applications.
By DesignGateway Co., Ltd.
