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High-Reliability FPGA Design Services
Installing functionality against soft error Implementing isolation to reduce error Support for neutron irradiation tests and consulting for soft error measures
By Hitachi Information & Telecommunication Engineering, Ltd.
HiPrAcc™ CS200D Dual-Agilex® Computational Storage Module
Highest performance PCIe Computational Storage Accelerator card with two Intel Agilex AGF027 FPGAs. up to 64TB on-card NVMe storage (8x M.2 SSDs) and Gen4 PCIe switch (Broadcom) interconnect.
By Hitek Systems LLC
HiPrAcc™ NC220 Low Profile PCIe Accelerator Card
Low-profile PCIe accelerator for data centers and edge AI, with up to 400 Gbps Ethernet, x16 PCIe Gen4, Agilex® 7 FPGAs (006 through 027 density), 24/12 GB DDR4 and SMB PPS sync input
By Hitek Systems LLC
HiPrAcc™ NCS200 Networked Computational Storage Card
FPGA accelerator card featuring Agilex® 7 Series FPGA with x16 Gen4 PCIe, 4x 100G networking interfaces, four on-card Gen4 M.2 NVMe SSDs (22110 and 2280) and two DDR4 UDIMM/RDIMM/LRDIMM slots — ideal for SmartNIC, computational storage and signal/image processing.
By Hitek Systems LLC
HiPrAcc™ NCS280-I CXL/PCIe Gen5 Accelerator
High performance CxL/PCIe Gen5 accelerator with R-Tile, dual QSFP28 based Ethernet networking, and dual on-card Gen4 M.2 NVMe SSDs
By Hitek Systems LLC
HLS, OpenCL, and RTL for AI Inference and Acceleration
This advanced course develops the skills to design, optimize, and integrate custom AI inference accelerator kernels using Altera HLS Compiler Pro, the Altera FPGA SDK for OpenCL, and RTL/SystemVerilog on Altera FPGAs.
By FPGA Authority
HMAC-SHA256 accelerator
Chevin Technology’s HMAC‑SHA256 cryptographic accelerator provides fast, secure generation and verification of message authentication codes, enabling trusted communication between senders and receivers. Implemented as an all‑RTL solution, it efficiently computes SHA‑256 hashes and HMAC codes for messages of any length, supporting multiple parallel data streams limited only by available memory. It is ideal for high‑security, high‑throughput applications—such as cybersecurity, defense, and aerospace—where CPU‑based solutions cannot meet performance and security requirements
By Chevin Technology Limited
HPS Peripherals, Drivers & Device Tree Development
Building on Linux BSP fundamentals, this course dives deep into Linux kernel driver development for HPS peripherals and custom FPGA IP on Altera SoC devices.
By FPGA Authority
HSDLC: HDLC & SDLC Protocol Controller Core
The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.
By Computer Aided Software Technologies, Inc (dba CAST)
