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JPEG-XL-E JPEG XL Encoder

The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery. Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions.

KEIm-A5ESoM

The KEIm-A5ESoM is a System-on-Module (SoM) powered by Agilex® 5 SoC FPGA E-Series. The SoM board is equipped with 4GByte LPDDR4 memory for HPS, dual channels of 4Gbyte LPDDR4 memory, 32GByte eMMC memory for storage, 2Gbit QSPI flash as configuration memory.

KEIm-A5ESoM Mini

The KEIm-A5ESoM Mini is a System-on-Module (SoM) powered by the Agilex 5 SoC FPGA E-Series. The module features 4GByte of LPDDR4 memory, 32 GByte eMMC storage, and 1 Gbit QSPI flash memory used as the configuration ROM.

KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)

KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)

KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)

KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)

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KJN-XL1_ENC(JPEG)

Our "KJN-XL1_ENC" is a latest JPEG standard, offering a JPEG IP core that achieves both high compression and high image quality.

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KRM-10A9W027

industrial grade SoM based on Agilex® 9 DirectRF AGRW027R28A2I2V

L/H-Tile PCIe* Hard IP

L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes.