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KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)
KiviPQC-Box - Post-Quantum Key Encapsulation and Digital Signature IP Core (ML-KEM und ML-DSA)
By KiviCore
KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)
KiviPQC-DSA - Post-Quantum Digital Signature IP Core (ML-DSA)
By KiviCore
KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)
KiviPQC-KEM - Post-Quantum Key Encapsulation IP Core (ML-KEM)
By KiviCore
KJN-XL1_ENC(JPEG)
Our "KJN-XL1_ENC" is a latest JPEG standard, offering a JPEG IP core that achieves both high compression and high image quality.
By Shikino High-Tech CO.,LTD
KRM-10A9W027
industrial grade SoM based on Agilex® 9 DirectRF AGRW027R28A2I2V
By Knowledge Resources GmbH
L/H-Tile PCIe* Hard IP
L/H-Tile are each an FPGA companion tile that supports PCI Express* configurations up to PCIe 3.0 x16 in Endpoint (EP) and Root Port (RP) modes.
By Altera
L8051XC1: Legacy-Configurable 8051-Compatible Microcontroller IP Core
The L8051XC1 is an MCS®51-compatible microcontroller core designed to match the timing and peripherals of legacy 8051-based systems. It supports instruction execution every 12, 6, or 4 clock cycles and includes user-selectable architectural extensions such as multiple data pointers, a multiply/divide unit, and a power management unit. The core can be coupled with peripherals that match the behavior of those from legacy vendors like Intel, NXP, Infineon, Maxim, and TI. Several pre-configured versions are available, along with options for customization. It supports legacy code and modern development through CAST’s on-chip debugging features and compatibility with IAR Embedded Workbench and Keil uVision™ IDEs. With design experience dating back to 1997 and hundreds of 8051 IP customers, CAST ensures that the core is optimized for easy ASIC/FPGA reuse. It is strictly synchronous, with positive-edge clocking and no internal tri-states. At 65nm, the core uses just 7.9K–20K gates.
By Computer Aided Software Technologies, Inc (dba CAST)
LDPC for 5G NR (Silicon Proven IP for Altera Devices)
This IP core features a programmable LDPC decoder using the Min-Sum algorithm, designed for 5G NR performance. It supports HARQ with LLR accumulation and early iteration exit for enhanced decoding efficiency. Runtime-configurable iterations and low latency make it ideal for 5G baseband integration.
By Mobiveil Inc.
LDPC for eMMC (Silicon Proven IP for Altera Devices)
Mobiveil’s LDPC for eMMC offers robust error correction and flash endurance in a compact, low-power footprint. It is tailored for smartphones, tablets, and enterprise SSDs requiring scalable, high-reliability flash storage. The IP meets performance needs while extending memory life significantly.
By Mobiveil Inc.