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Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design
The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.
By Missing Link Electronics
LVDS Tunneling Protocol and Interface IP
LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.
By Altera
LZ4SNP-C: LZ4/Snappy Data Compressor
LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compression standards. The core receives uncompressed input files and produces compressed files. No post-processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers.The core’s flexible architecture enables fine-tuning of its compression efficiency and throughput to match the requirements of the end application. More than one block compression engine can be internally instantiated to scale throughput, while block and history window sizes can be adjusted to optimize either hardware resources utilization or compression efficiency.
By Computer Aided Software Technologies, Inc (dba CAST)
LZ4SNP-D: LZ4/Snappy Data Decompressor
LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data.The core features fast processing with low latency and high throughput. In its default configuration, LZ4SNP-D outputs up to 7.8 bytes of decompressed data per clock cycle and can be clocked at frequencies exceeding 1 GHz in modern ASIC technologies. Designers can scale the throughput by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The processing latency is approximately 30 clock cycles.The decompression core operates on a standalone basis—offloading the host CPU from the demanding task of data decompression—and has been designed for easy integration and use. No preprocessing of the incoming compressed files is required, as the core parses the file headers, and checks the input files for errors.
By Computer Aided Software Technologies, Inc (dba CAST)
M.2-FMC Adapter Board for NVMe SSD (AB17-M2FMC)
This adapter board converts 8 FMC high-speed differential signals (DP0–DP7) into two 4-lane PCIe® standard M.2 interfaces. It is compatible with Altera FPGA evaluation boards featuring an HPC (High Pin Count) FMC connector, allowing users to evaluate the NVMe-IP core from Design Gateway.
By DesignGateway Co., Ltd.
M.2-PCIe Adapter Board for PCIe Gen5 SSD (AB19-M2PCI)
This adapter board converts 16-lane PCIe® interface to four 4-lane PCIe standard M.2 interfaces, supporting PCIe Gen5 speeds. This adapter can be applied to FPGA evaluation boards from Altera so that user can evaluate NVMe™ series IP Core operation and can use for prototype development platform.
By DesignGateway Co., Ltd.
MAC-SeC-MG
The MAC-SEC-MG from CAST is a high-performance hardware MACsec IP core designed to provide robust security for 2-16.75 Gbps Ethernet networks. It fully implements the IEEE 802.1AE-2018 and IEEE 802.1AEbw standards, supporting GCM-AES and GCM-AES-XPN encryption modes with 128- and 256-bit keys. The core features a 128-bit wide data path and operates at line speed in full-duplex mode, ensuring low-latency and secure communication. It supports up to 64k security associations and multiple security channels and entities, making it suitable for both simple LAN deployments and complex WAN architectures. MAC-SEC-MG integrates easily with Ethernet MACs, including CAST’s Low-Latency eMAC, and can work alongside networking protocol stacks such as UDP/IP and TCP/IP. Its standardized interfaces and high configurability make it ideal for automotive, industrial, and IoT edge applications, providing reliable encryption, authentication, and integrity protection for sensitive Ethernet traffic.
By Computer Aided Software Technologies, Inc (dba CAST)
MAC/PCS
Chevin Technology’s IEEE 802.3by‑compliant 10/25/40/100G MAC/PCS delivers high‑speed, full‑duplex Ethernet connectivity with efficient resource utilisation in Altera FPGA designs. It enables seamless integration of protocols such as TCP/IP and UDP while providing advanced features like low‑latency cut‑through operation, CRC32 error checking, and throughput optimisation. Supported by reference designs and expert engineering services, it offers a reliable and flexible solution for high‑performance networking applications.
By Chevin Technology Limited
MACsec FPGA IP
The MACsec FPGA IP core is a fully configurable soft IP that implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018). MACsec provides data confidentiality and integrity for the Ethernet protocol and is commonly used to secure network traffic in a variety of different applications.This IP core makes use of the Symmetric Cryptographic Accelerator (SCA) Hard IP, which is available in select Agilex 7 F-series and I-series devices. With the SCA, Altera's MACsec IP core can achieve 100 Gbps full-duplex line rates. Note that the SCA can also be used as a stand alone cryptographic accelerator.
By Altera